@DaveAE

You just enjoy in your holiday, you undoubtedly deserved it.

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You can crack anything with your head, even the head itself.
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...proud AOS user since 1993
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So what happened with this ? Is there any working solution ?

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Rock lobster bit me. My Workbench has always preferences. X1000 + AmigaOS4.1 FE
"Anyone can build a fast CPU. The trick is to build a fast system." -Seymour Cray

@Tomppeli

Omg, the thread came alive!
No solution, unless you buy a CMI card (and don't have a Radeon 7000!!) or other non-emu10kx soundcard. We don't know why it happens either, since every theory has its counter-example. Don't count on a solution either.

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Audio Evolution
http://www.audio-evolution.com

@DaveAE

I did a bit of digging around after I was asked to take a look at this and I have a few observations to report. I do not claim to have the solution. I am providing an analysis based upon a study of the following materials:

Articia S datasheets (downloaded many years ago from MAI),
The Teron Mini reference design,
Some VIA 686 documents and Linux drivers,
UBoot source code, specifically, the u-boot-1.1.2\board\MAI\AmigaOneG3SE directory.

What surprised my was that the Via 686B handles the AGP/Graphics interrupt. In the Teron Mini design, it was tied to PCI INT C. The MAI Articia S datasheet explains that you need an external interrupt handler, the VIA 686B provides this.

The graphics interrupt, for want of a better word, will be persistent and needs to be handled at a high priority.

If improvements can be made to the PCI interrupt handler, that could, in theory, help the system.

The UBoot code dates back to 2004, but the Via 686B code does not appear to have any of the recommendation, that linux uses to fix the bugs. The bug fixes primarily deal with PCI latency timer and arbitration issues. The Linux recommendation is to set the PCI bus latency to 0 and the Abitration timer to 96 clock cycles.

The PCI latency factor and Arbitration timer registers affect the throughput of the PCI bus. A larger arbitration timer allows larger transfers and higher throughput but increases system latency as another device has to wait longer to access the bus and interrupts take longer to process. These values are invariably tweaked on a system by system basis. There are no hard and fast rules on this.

From the PCI specification (sorry if the formatting gets screwed up).

Data Phases Bytes Total Clocks Latency Timer Bandwidth Latency
Transferred (clocks) (MB/s) (μs)
8 32 16 14 60 0 .48
16 64 24 22 80 0.72
32 128 40 38 96 1.20
64 256 72 70 107 2.16

The Latency timer is at adddress $0D of the PCI standard register set. The Maximum Latency and Minimum Grant registers are at addresses $3F and $3E respectively.

This may not be anything but the default serial port setting of 9600 BPS triggers an interrupt after only one byte is received. This is fine for a debug port, my worry is if software changes the BAUD rate but does not change the FIFO settings, the serial port becomes an interrupt hog.

Ok after all my goings on, if the system is having trouble responding to interrupts, you will get breaks in data transfers of Music, Video, Audio etc and it all comes down to PCI bus settings. Tweaking the interrupt handling, has from experience fixed most problems.

Oh, there is an Easter Egg in Uboot.

Hope this helps stimulate some more ideas.

Ian

@stedy

Wow ... Thanks


( did something just go whooshing over my head ?)

I'm sure someone will find that info helpful !!

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I dont suffer from Insanity - I enjoy it

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@stedy

Quote:

Oh, there is an Easter Egg in Uboot.

Is that the Commodore 64 screen-like Easter Egg?

Sounds like you've done a lot of research on the Interrupt issues. I wish I
could add something useful but I can't!

Have you tried fiddling around with the settings like you mentioned, to test
different settings, or does this have to be done in UBoot? (or is it more
complex than this?)

Cheers,
Bean.

Last edited by Bean on 15-Apr-2006 at 01:00 AM.

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OS4.1 + SAM Flex
RIP my A1XE.. that used to have an appetite for batteries!

@stedy

Omg, this thread came alive again!

Anyway, thanks for reporting your findings. I have fiddled with the latency and grant registers on the SB Live and 3com ethernet chip without any luck. IIRC, I didn't try it on the via686b itself though. Perhaps it's worth a try indeed.

Thanks

Davy

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Audio Evolution
http://www.audio-evolution.com

@DaveAE

Let us know please

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ikir

@Bean

Yes the C64 screen is the Easter Egg. I prefer the real ones this time of year :)

I don't have an AmigaOne so could not try these things myself.

@DaveAE

I was a bit surprised to find that the 686B controls the PCI bus arbitration but I have since worked with an AMD device that uses the same approach so it is not uncommon in the X86 world.

I learnt about the latency registers and system performance by reading the book PCI Express system architecture, which is a good read.

I will help where I can with information, I know have some additional Via 686B documents which I hope to read through soon.

Must go.

Ian

@all

I have been nagging a lot about this the past year, but I must say that I have not managed to get a single lockup of that kind since upd4!
I have an SB Audigy.

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- Don't get fooled by my avatar, I'm not like that (anymore, mostly... maybe only sometimes)
> Amiga Classic and OS4 developer for OnyxSoft.