@KimmoK

Link please

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retired

@AmigaBlitter

I post all kinds of findings to here:
http://amigaworld.net/modules/newbb/viewtopic.php?mode=viewtopic&topic_id=35140&forum=33&start=200&viewmode=flat&order=0#733753

NGC on page 10, one 20*e6500 core example on page 24, etc, etc...
http://cache.freescale.com/files/training/doc/dwf/DWF13_APF_NET_T0795.pdf
UPDATE: page 11 has nice comparisson of SandyBridge, ARM A15, MIPS EC4400 and e6500. (shows the strong points of PPC)

I hope there pops up some new public document about the NG PowerPC core.

Last edited by KimmoK on 16-Jul-2014 at 08:53 AM.
Last edited by KimmoK on 15-Jul-2014 at 01:38 PM.

_________________
- KimmoK
// For freedom, for honor, for AMIGA
//
// Thing that I should find more time for: CC64 - 64bit Community Computer?

@KimmoK

Power.org roadmap doesn't mention any new PPC cores bar Power 8.
And I haven't seen anything on the subject officially from Freescale either.

Coremark is not the most reliable benchmark.

Cavium intends to introduce 48 core ThunderX in H1 of 2015.
Nvidia and Samsung might also join the party with their hardware.
Intel will release a 72 core Knights Landing in 2015, this time as a standalone CPU as well as PCIe accelerator card.

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@WolfToTheMoon

Our ARM v8 plans are on the way - cannot disclose details but first compute module will be much less performant than the T4240 part. I estimate it will take industry between 3 and 5 years from now (July 14) to get high performance ARM v8 parts. This requires custom core design (not the A57).

I cannot legally disclose T4240 performance numbers at this time. Working on getting that permission . I only can say that the T4240 performance is quite impressive.

Note that first T4240 silicon (aka rev1) had a memory performance bug which is fixed in rev2, which only very recently became available from FSL (that is how Freescale is abbreviated..). That is why I have an RDB with rev2 as my QDS runs with rev1.

Ronald

@RonaldGadget

Quote:

I only can say that the T4240 performance is quite impressive.

Interesting, really interesting

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retired

@RonaldGadget

Quote:

I estimate it will take industry between 3 and 5 years from now (July 14) to get high performance ARM v8 parts. This requires custom core design (not the A57).

Well, by your own standard, such a core already exists for almost a year, but it's locked inside Apple's ecosystem :). Nvidia's Denver CPU might be what you're describing, and it's not 3 years away. Qualcomm is also developing their own ARMv8 compliant core and I bet it's not 3 years away either.

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Quote:

NutsAboutAmiga wrote: Some small differences between different generation of CPU models exists, when cpu get a illegal instruction hit, then this are emulated by the OS, not unlike how its done on MC68060 when you run a program with some instruction it does not have. Some CPU's have some special instructions like “ISEL”, I really wanted to use that one, when I wrote some PowerPC assembler. Its bit like how this works in C code. x=(istrue ? 1 : 2);

Standard ISA implementations are as important as standard ISAs. Unfortunately, chip manufacturers think they gain an advantage even today by dropping "used" hardware instructions and making annoying incompatible customizations. Yes, most Freescale PPC processors are for embedded customers but I would expect that they could decide on a core of PPC instructions (partial PPC ISA) to support in all embedded processors. It would make programming, compiler support and OS support much easier and better. As it is, no ISEL for you but ARMv8 gets all these conditional instructions:

CSEL Wd, Wn, Wm, cond
CSEL Xd, Xn, Xm, cond
CSINC Wd, Wn, Wm, cond
CSINC Xd, Xn, Xm, cond
CSINV Wd, Wn, Wm, cond
CSINV Xd, Xn, Xm, cond
CSNEG Wd, Wn, Wm, cond
CSNEG Xd, Xn, Xm, cond
CSET Wd, cond
CSET Xd, cond
CSETM Wd, cond
CSETM Xd, cond
CINC Wd, Wn, cond
CINC Xd, Xn, cond
CINV Wd, Wn, cond
CINV Xd, Xn, cond
CSINV Xd,Xn,Xn,invert(cond).
CNEG Wd, Wn, cond
CSNEG Wd,Wn,Wn,invert(cond).
CNEG Xd, Xn, cond
CCMN Wn, Wm, #uimm4, cond
CCMN Xn, Xm, #uimm4, cond
CCMN Wn, #uimm5, #uimm4, cond
CCMN Xn, #uimm5, #uimm4, cond
CCMP Wn, Wm, #uimm4, cond
CCMP Xn, Xm, #uimm4, cond
CCMP Wn, #uimm5, #uimm4, cond
CCMP Xn, #uimm5, #uimm4, cond

It makes sense on ARM of course since ARMv8 and PPC are both load/store architectures, support 64 bits and have 32 gp registers. What was the difference again? Oh yea, ARMv8 gets to have "many" hardware conditional instructions at least until ARM changes their ISA deprecating instructions and creating hundreds of different ISA variants as they are known for also. One of the big appeals of ARMv8 is that it's a new ISA that hasn't been screwed up yet. Did they have the foresight not to make the ISA too complex considering it targets low power processors also? No. Compilers won't take advantage of many of the new instructions and then processors won't put them in hardware because they aren't being used. The ARMv8 fans will tell me how it will be different this time just as the PPC fans were sure that compiler support would spell the end to CISC processors. Rinse and repeat the same mistakes they do ad nauseam. Motorola/Freescale hasn't ever been but blundering idiots at anything to do with ISAs. The pinnacle of their organic ISA achievements was to simplify to the point of uselessness with the MCore ISA, at a time when ARM could have used some competition with power efficient processors. They also cut, abandoned and anti-marketed their 68k line at a time when the 68060 solved practically all the CISC problems giving the baton to Intel to turn an inferior CISC ISA into the worlds most powerful processors. Freescale seems happy enough letting everyone else lead in technology.

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RonaldGadget wrote: I am amazed at the discussion that is taking place in this forum... One the the insights that I got to some time ago: The ISA does not matter. What matters is the ecosystem. My latest insight: Compute is free -- data is not.

The ISA is less important today (it still matters!) but half implemented, evolving and cut down ISAs are a pain. Is it really that difficult to adopt a core of instructions and stick with it for all implementations of that ISA? This is where Intel leads with their inferior x86/x86_64 ISA (although modern CISC is under rated). This is a big part of the reason why their ATOM SoC processors will continue to gain market share for smart phones/pads/netbooks/gadgets while Freescale doesn't even have a competing product without paying licensing fees. This is why Intel will continue paying a healthy stock dividend in the next financial crisis while Freescale will have to fire half their people and buy back their debt for pennies on the dollar to avoid bankruptcy again. Enough ranting. It's not like the Freescale management get it or they would be leading instead of following.

@WolfToTheMoon

>And I haven't seen anything on the subject officially from Freescale either.

Perhaps you have not looked. On post 82 I linked a freescale (y2013) document with NGCore.

>Coremark is not the most reliable benchmark.

I think it's one of the most reliable "core" benchmark. Very widely used, even though it's "new".

>Cavium intends to introduce 48 core ThunderX in H1 of 2015.

We will see how they come out. I have some experience of Cavium chips and the ones I became familiar were not earth shaking inventions. It could be that the 48core thunderX is not yet enough to beat e6500 based multicore products (in performance/watt).

>Intel will release a 72 core Knights Landing in 2015, this time as a standalone CPU as well as PCIe accelerator card.

As performance/watt is the key in this thread, intel might neither be able to compete with T4240 in DOME kind of computing use. (perhaps they target to become competitive with POWER in the high performance supercomputing)

Coremark/Mhz (With Dome's 1500-3000 core unit, one can not run cores at 3Ghz.)
i7 - 41 (12 threads)
T4240 - 104 (24 threads)


>...Apple's ecosystem ... Nvidia's Denver ... Qualcomm is also ...

To my understanding, Cavium is the only one (publickly) trying to make (custom?) ARM cores that can handle more than 8 cores in multicore config. Cell phone chips do not count.

Last edited by KimmoK on 16-Jul-2014 at 07:55 AM.

_________________
- KimmoK
// For freedom, for honor, for AMIGA
//
// Thing that I should find more time for: CC64 - 64bit Community Computer?

@KimmoK

Quote:

Perhaps you have not looked. On post 82 I linked a freescale (y2013) document with NGCore.

there's no details or ETA. It's a paper core. I can do one too.
Considering how T4xxx was late to market and that it is yet to achieve it's max design freq. of 2.5 GHz, I think it will be a while till we see any completely new cores from Freescale.

Quote:

As performance/watt is the key in this thread, intel might neither be able to compete with T4240 in DOME kind of computing use. (perhaps they target to become competitive with POWER in the high performance supercomputing)

Knights Landing will be a 14 nm product, using modified Silvermont cores(which typically are around 1 W TDP on 22 nm)

They also have 10 core Ivy-Bridge based Xeons that top out at 60 W TDP, same as T4240. Ivy Bridge is faster core vs core.

Quote:

To my understanding, Cavium is the only one (publickly) trying to make (custom?) ARM cores that can handle more than 8 cores in multicore config. Cell phone chips do not count.

Broadcom and Applied Micro are also doing it. Qualcomm expressed interest in that market also.

Last edited by WolfToTheMoon on 16-Jul-2014 at 07:29 AM.

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@WolfToTheMoon

Quote:

Well, by your own standard, such a core already exists for almost a year, but it's locked inside Apple's ecosystem :). Nvidia's Denver CPU might be what you're describing, and it's not 3 years away. Qualcomm is also developing their own ARMv8 compliant core and I bet it's not 3 years away either.

I do not know what Apple's plans are. Do you? Yes, my son carries 64 bit ARM in his pocket... OK, I wrote 'parts' - I should have written 'systems'. With 'high performance' I mean on par with X86 based systems.

Ronald

@RonaldGadget

They will never be on par with Intel simply because of process advantage Intel continues to enjoy.

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@matthey

Quote:

Standard ISA implementations are as important as standard ISAs. Unfortunately, chip manufacturers think they gain an advantage even today by dropping "used" hardware instructions and making annoying incompatible customizations.

Its a trade off, less power consumation and heat,

Quote:

It would make programming, compiler support and OS support much easier and better

Many things can be just recompiled, Linux is open source, it might not be ideal for AmigaOS it but it does not seam to be big issue.

ISEL has FSEL and VSEL equivalent, V is for VMX (AltiVec), the VSEL might be best instruction to use on my CPU, more to the point I suck at wring AltiVec assembler code.

If I worked with floating point then FSEL might have worked, but converting from INT to FLOAT in assembler is not that simple as it should be, (It seam there is no way of moving from float register to int register with out putting it in RAM first.) so there was no gain for me to use FSEL one.

It might be that might been able to work around my problem with a indexed read instead but anyway annoying. I'm hopeful table stay in data cache, for period of time I needed it.

ARM is irrelevant for AmigaOS4, because of legacy anyway I'm shore Hyperion has better things to do right now.

Last edited by NutsAboutAmiga on 16-Jul-2014 at 08:28 AM.
Last edited by NutsAboutAmiga on 16-Jul-2014 at 08:21 AM.

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@WolfToTheMoon

>Considering how T4xxx was late to market and that it is yet to achieve it's max design freq. of 2.5 GHz,

I think T4 was never planned to run at 2.5Ghz. I Think single core T5 was planned to have e6500 running @ 2.5Ghz.
Running 7 stage pipeline chip @ 2Ghz is not a simple task. I think no-one else has done it either?

It would seem there will not be T5 @ 2.5Ghz with e6500.
If they think there is demand for 2.5Ghz PPC chips they might need to do it with NGC & perhaps with longer pipeline.

>I think it will be a while till we see any completely new cores from Freescale.

They have no hurry as sales of e6500 core chips just started.
And we (amiga niche) have no hurry either as we are a few generations behind anyway, untill e5500 powered HW is out.

About intel @ DOME kind of use... intel needs to stay ahead on production technology as they drag the legacy x86 support with their cores. With the same manufacturing process intel would loose in power usage vs getting real work done against newer ISA chips. Only time will tell if they manage in future. (I'm not betting against them.)
(IBM 7nm process plans...)
(( not totally unrelated to DOME ... browse these ))

Last edited by KimmoK on 16-Jul-2014 at 09:23 AM.

_________________
- KimmoK
// For freedom, for honor, for AMIGA
//
// Thing that I should find more time for: CC64 - 64bit Community Computer?

@KimmoK

Quote:

About intel @ DOME kind of use... intel needs to stay ahead on production technology as they drag the legacy x86 support with their cores

not true... the legacy part is such a small percentage of today's cores, it doesn't really matter.

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@WolfToTheMoon

I read that legacy support is the size of FPU on intel core. With thousands (and tens of thousands) of cores in DOME kind of use it might become more relevant. (unless legacy stuff consume no power when running pure x64 code)

@thread

btw. One reason to be "friends" with DOME developing ppl, is to get possibility to use their idling development boards for PPC OS work for certain SoCs.

Last edited by KimmoK on 16-Jul-2014 at 01:05 PM.
Last edited by KimmoK on 16-Jul-2014 at 01:02 PM.

_________________
- KimmoK
// For freedom, for honor, for AMIGA
//
// Thing that I should find more time for: CC64 - 64bit Community Computer?

@WolfToTheMoon

Quote:

They will never be on par with Intel simply because of process advantage Intel continues to enjoy.

Ohhh - I so challenge you with your statement.... (This is my personal opinion). Watch the CMOS roadmap extremely carefully. Going from 14nm to 10nm node, 'interesting' things happen. As I said, 3 - 5 years.

Ronald

@all

Here is a quick update (15 Aug 14).

Got Fedora 20 working on Rev 2 T4240. DB2 installed and working. 4 way cluster up and running.
See pictures here

On our own designed board, still working on debugging the power supply.

Ronald

Quote:

KimmoK wrote: >Coremark is not the most reliable benchmark. I think it's one of the most reliable "core" benchmark. Very widely used, even though it's "new".

It's not. It's ONE benchmark, and it doesn't even use SIMD, if I remember correctly.
Quote:

Quote: Intel will release a 72 core Knights Landing in 2015, this time as a standalone CPU as well as PCIe accelerator card. As performance/watt is the key in this thread, intel might neither be able to compete with T4240 in DOME kind of computing use. (perhaps they target to become competitive with POWER in the high performance supercomputing)

Currently the Knights Corner-based Xeon Phi gives around 2TFLOPS in single precision floating point, and 1TFLOP in double precision. Do you know of any PowerPC CPU that can give similar results?

And Knights Landing will TRIPLE that numbers.

The situation is quite simple: Intel is able to compete even on HPC area, previously dominated by PowerPC. And now you can find Intel's processors tablets, smartphones, and even on Arduino devices (Galileo), with comparable power consumption.

Is there anything similar which is PowerPC-based?

Quote:

WolfToTheMoon wrote: @KimmoK Quote: Perhaps you have not looked. On post 82 I linked a freescale (y2013) document with NGCore. there's no details or ETA. It's a paper core. I can do one too. Considering how T4xxx was late to market and that it is yet to achieve it's max design freq. of 2.5 GHz, I think it will be a while till we see any completely new cores from Freescale. Quote: As performance/watt is the key in this thread, intel might neither be able to compete with T4240 in DOME kind of computing use. (perhaps they target to become competitive with POWER in the high performance supercomputing) Knights Landing will be a 14 nm product, using modified Silvermont cores(which typically are around 1 W TDP on 22 nm)

And don't forget that Skylake comes next year, which a completely new architecture.
Quote:

They also have 10 core Ivy-Bridge based Xeons that top out at 60 W TDP, same as T4240. Ivy Bridge is faster core vs core.

http://www.cwcdefense.com/media-center/articles/avx-a-leap-forward-for-dsp-performance-.html

I already posted this link some time ago, but "strangely" no PowerPC aficionado replied. Who knows why...

BTW, Skylake will bring AVX-512: it will double the SIMD performance (and even more, IMO, due to a lot of new good stuff put in this new ISA).

Quote:

With 'high performance' I mean on par with X86 based systems.

We will see when/if it happens. Currently numbers show a very different picture.

Quote:

WolfToTheMoon wrote: @RonaldGadget They will never be on par with Intel simply because of process advantage Intel continues to enjoy.

It's not only the process advantage. ISA matters; a lot. Take a look at AVX vs Altivec, for example.

Quote:

KimmoK wrote: About intel @ DOME kind of use... intel needs to stay ahead on production technology as they drag the legacy x86 support with their cores.

You don't know of what you're talking about. The so called "x86-tax" has a VERY LIMITED impact, and that's from long time.

Maybe you're still stick to the PentiumPro era...

Quote:

With the same manufacturing process intel would loose in power usage vs getting real work done against newer ISA chips.

Have you any concrete data about, or are you just talking about the classic internet rumors / legends / myths?
Quote:

Only time will tell if they manage in future. (I'm not betting against them.)

We'll see.

Quote:

WolfToTheMoon wrote: @KimmoK Quote: About intel @ DOME kind of use... intel needs to stay ahead on production technology as they drag the legacy x86 support with their cores not true... the legacy part is such a small percentage of today's cores, it doesn't really matter.

Not even for today's cores: the situation is changed some time ago, when chips have moved from millions to hundreds transistor. Nowadays the situation is much better, because we have billions of transistors packed.

Quote:

KimmoK wrote: @WolfToTheMoon I read that legacy support is the size of FPU on intel core.

Where? Can you provide some link? Because that's TOTALLY wrong and I'd like to laugh a bit.

BTW, the old x87 FPU has LITTLE part on the whole "legacy" area.
Quote:

With thousands (and tens of thousands) of cores in DOME kind of use it might become more relevant.

Thousands? You have just 12 cores on the most powerful PowerPC CPU.

By comparison, the current Xeon Phi systems have 61 cores (and 244 hardware threads). Yes, "x86-tax" included.
Quote:

(unless legacy stuff consume no power when running pure x64 code)

The power consumption is very very limited. And, yes: 80% of the time there's NO power consumption due to the legacy stuff. Take a look at this: http://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/2

It's quite clear that you don't know what are you talking about...

Quote:

RonaldGadget wrote: @WolfToTheMoon Quote: They will never be on par with Intel simply because of process advantage Intel continues to enjoy. Ohhh - I so challenge you with your statement.... (This is my personal opinion). Watch the CMOS roadmap extremely carefully. Going from 14nm to 10nm node, 'interesting' things happen. As I said, 3 - 5 years. Ronald

The 10nm node will come in the next two years, according to the latest Intel's roadmap. And there are plans to further go down.

If you have some new about this, you can post it.

@cdimauro

Quote:

If you have some new about this, you can post it.

I can post Facts only when they are *facts* and not expectations on newsblurbs, and then only when they are non-confidential. For the moment: wait....

@RonaldGadget:

I'm in a better position from this point of view, but the same applies to me: I cannot disclose confidential information.

We can comment when it will become public (albeit some have been published just some days ago).