@ppcamiga1

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Of course not. On ARM constans, offsets are compiled in little endian mode with instructions, and stay in little endian format after switch to big endian.

A small example. The following two instructions load 32-bit constant into register:

movz w1, #0xbeef
movk w1, #0xdead, lsl #16

After these two are executed register w1 contains the value 0xdeadbeef. Followed with a store instruction:

str w1, [x0]

which will save the 0xdeadbeef 32-bit word at address given in register x0.

Now, the instruction stream for this three instructions is: a1 d5 9b 52 e1 dd b7 72 01 00 00 b9
Since in big endian mode the instructions are still stored in LE byte order in memory, the very same code can be executed in both modes of AArch64 cpu:

1. When ARM cpu is running in little endian mode, the register W1 will contain 32-bit word 0xdeadbeef. The memory pointed by register X0 will contain following bytes: ef be ad de, which correspond to the W1 value written as LE.

2. When ARM cpu is running in big endian mode, the register W1 will contain 32-bit word 0xdeadbeef. The memory pointed by register X0 will contain following bytes: de ad be ef, which correspond to the W1 value written as BE.

Now, tell me where the problem with recompilation or code modification occurs.

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Of course I'm right

Because you say so?

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and You lie

There is no reason to insult me.