@Mechanic

Quote:

Time and again the words impossible and 'can't be done' have proven to be just that, words.

If that is indeed the case, it merely shows that whoever uttered those words used them wrongly --- yes, it is popular, though stupid, to say "impossible" instead of "I have no friggin idea how to do it". "Impossible" means "I have an incontrovertible argument showing that it cannot be done".


Let me demonstrate:

"Easy" --- 'find three integers c>=b>=a such that a^2+b^2=c^2"

"Definitely possible, but tedious" --- 'find the sum of a for all sets of three positive integers c>=b>=a such that a^2+b^2=c^2 and 1,000,000,000>=a+b+c'[1]

"Impossible" --- 'find three positive integers c>=b>=a, a,b,c prime, such that a^2+b^2=c^2'[2]

"Do trust other's statement of impossibility" --- 'find three positive integers c>=b>=a such that a^3+b^3=c^3'. I could presumably follow the existing proof, but have not done so.

"Must trust other's statement of impossibility" --- 'find three positive integers c>=b>=a such that a^20000+b^20000=c^20000'. The maths for proving this are beyond me, but I know a proof exists which has been thoroughly vetted by the experts, and has been judged valid

"No idea, may be impossible, may not be" --- 'find three positive integers a,b,c such that a^2+b^3=c^4'. It is quite likely that the experts know whether this can be done or not, but unlike the previous two cases, I am not aware of their knowledge.



You are welcome to try your hand on doing any of the "impossible" things; Trying to do so can be highly educational, as well as entertaining. However, if you want to have any chance of success, you should stay away from them....

Similarly, trying to use the XCore chip on the X1000 board for speeding up 3D rendering in any meaningful way can be highly educational; If you want to actually find a use for the XCore chip, though, you should attempt something that it is not demonstratibly unsuited for.


[1]: This is actually a nice example --- it is obvious that a program to calculate this is trivial to write, simply by iterating each of a,b,c from 1...10^9, and checking whether any such combination is a Pythagorean triple. It's equally obvious that doing so will not produce the result in a practical time. However, the fact that it can be shown that the result *can* be calculated at all means there is a pretty decent chance it can be calculated efficiently. The answer, assuming my
quick-n-dirty program does not contain some screwup, is 108294675386106124, calculated in 2.35 seconds.

[2]: The reason this is impossible is thus: a,b,c cannot all be odd, because the sum of two odd numbers is even. Thus, at least one of a,b,c is even. But there is only one even prime, which is 2. As there are no primes smaller than 2, that means we would require a=2. So the problem becomes "find b,c primes such that 4+b^2=c^2". This implies c>b; Call c=b+n, then 4+b^2=(b+n)^2=b^2+2bn+n^2. Given that b>=2 and n>=1, 2bn+n^2>=5. However, it would need to be 4 for the equality to hold. So there cannot be c>=b>=a prime such that a^2+b^2=c^2.

Last edited by umisef on 26-Jun-2010 at 05:28 PM.
Last edited by umisef on 26-Jun-2010 at 04:31 PM.
Last edited by umisef on 26-Jun-2010 at 04:30 PM.
Last edited by umisef on 26-Jun-2010 at 04:28 PM.

@umisef
I believe you can access the system main ram if you create a memory server, for off line rendering you don't need high bandwidth, additionally you could divide the screen into tiny tiles and assign one to each Xmos in the cluster (adding as much as needed).
Moreover what if they come out with a secoond generation chip that sports higher frequencies and and FPU? A mini cluster of those could be interesting too...

Last edited by DAX on 26-Jun-2010 at 04:43 PM.

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@Hyperionmp

Quote:

Umisef has no access to any unrestricted XMOS material nor their very interesting roadmap.

Umisef does indeed have access to all the unrestricted XMOS material. As does everybody else --- that's what "unrestricted" means after all.

XMOS's documentation download area has complete documentation for the XS1-L1 128; Everything from pinout, electrical characteristics, power consumption and so on, all the way to complete instruction set description, with complete instruction timings, thread scheduling algorithms, I/O timings and anything else someone would need to know to go from "my XS1-L1 chip arrived in the mail todo" to "Look, here is my fully functional piece of kit".

Your lame attempt to imply (again, without actually saying so) that there is some mysterious, amazing information in restricted material which you are aware of, is laughable given the depth and detail of the unrestricted material.


And I am baffled why you would consider the roadmap relevant. Whatever is on the roadmap won't change the specifications of the XS1-L1 128; And as that is the chip which is on the X1000 motherboard, the roadmap is entirely irrelevant for judging what the XCore chip on that motherboard is and is not useful for.

@umisef

Quote:

How hard is it to understand that a Transputer was a general purpose CPU ,,,

Its impossible to understand for people without any knowledge of system architecture. And people that believes in hypes und wonders will not only believe every announcement, no they will invent facts to the promised parts that will make the announcement even bigger.

cu

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I borrowed this comments from here (#27 & #28):
http://amigaworld.net/modules/newbb/viewtopic.php?topic_id=38873&forum=2&start=20&order=0

@DAX

Quote:

I believe you can access the system main ram if you create a memory server,

I believe you believe wrongly.

Quote:

for off line rendering you don't need high bandwidth,

Huh? For rendering, you need to calculate the intersection of view rays with the polygons (or other surfaces) that make up your scene. Thus, you need to be able to access your scene description, all the time, fast. The memory on the XS1-L1 is insufficient to hold real-life scene descriptions.

Quote:

additionally you could divide the screen into tiny tiles and assign one to each Xmos in the cluster

Yes, the calculations for the various view rays are what's usually referred to as "embarrassingly parallel". But for each tile (or indeed each ray), in order to calculate what parts of the scene it intersects with, you need the scene description.

Quote:

Moreover what if they come out with a secoond generation chip that sports higher frequencies and and FPU? A mini cluster of those could be interesting too...

Sure (as long as you replace "higher frequencies" with "more memory"). But a mini cluster of hypothetical future XCore chips is not what is going to be on the X1000, now is it? What's on the X1000 is going to be a 500MHz, single core XS1-L1.

@Hyperionmp

Quote:

Hyperionmp wrote: I wouldn't take his opinion on the XMOS chip very seriously.

Ack, you don't need opinions if you can read the facts!
The XMOS chip is a 10$ hype generator, you aa a manager type knows exactly what it is used for.

Last edited by Arko on 26-Jun-2010 at 06:08 PM.
Last edited by Arko on 26-Jun-2010 at 05:29 PM.
Last edited by Arko on 26-Jun-2010 at 05:27 PM.

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AmigaONE. Haha. Just because you can put label on it does not make it Amiga.

I borrowed this comments from here (#27 & #28):
http://amigaworld.net/modules/newbb/viewtopic.php?topic_id=38873&forum=2&start=20&order=0

@Hyperionmp

Quote:

I wouldn't take his opinion on the XMOS chip very seriously.

Why the FUD? If you think he's wrong, why not refute his claims with factual information? Point out where he's wrong, if you think he's wrong. IMO no one has contributed more facts and professionalism to this thread than umisef.

Resorting to comments like this, you end up looking desperate and unprofessional to all but the "true believers".

@umisef
wrongly? You are saying that the Xmos chip is isolated and not connected to the main system in any way or form? If it is than there is a way to access main memory, even if it will be at low bandwidth.

Wouldn't it be possible to fragment the scene description as well?

And if not, what about an hybrid solution? Where the Xmos cluster only process some data in order to "help" but not take care of the whole rendering process?

As for what's on the board, isn't the Xorro slot supposed to accept additional cores? I don't see why they couldn't use 2nd G chips as well there.

Moreover, the X1000 is no mainstream machine, who cares what Average Joe would think of the benefits of such weird solutions. The X1000 is just a gymn for developers (and an expensive toy for Amiga enthusiast), if they have a nice idea and doesn't play well with current architecture it will serve as a guideline for the X2000.

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@umisef

Quote:

umisef wrote: @Mechanic You are welcome to try your hand on doing any of the "impossible" things; Similarly, trying to use the XCore chip on the X1000 board for speeding up 3D rendering in any meaningful way can be highly educational;

I accept your proof for the definition of the word 'impossible'. At that point is where 'a different point
of view' kicks in.

Xena is a gateway to Xorro. Xorro is a gateway to other functions and then to a 1x PCIe slot. The PCIe
slot is........................................

3D on a flat screen is impossible. The limits are within us.

@DAX

Quote:

wrongly? You are saying that the Xmos chip is isolated and not connected to the main system in any way or form? If it is than there is a way to access main memory, even if it will be at low bandwidth.

The main memory in the X1000 is controlled by the memory controllers in the main SoC. So for the XCore to access main memory, it somehow needs to convince the SoC's memory controllers to do the job. Which means getting the request into the SoC.

The SoC does not have an external memory bus. It has PCIe lanes, which have full DMA access --- but the XCore does not have any facilities for hooking up to PCIe (PCIe lanes have a bit rate of 2.5Gb/s minimum, that's simply out of reach for XCore).
Apart from that, the main SoC has a few rather-low-bandwidth ports, none of which can be used directly to access the memory controllers. Yes, one could run a server on the main CPU which watches one of those ports for an incoming memory request, and then accesses the memory controller on the XCore's behalf, passing back the result through the port. However, the resulting memory bandwidth for the XCore would be very very low (I would be very surprised if you could reach double digits MB/s, and *wouldn't* be surprised if it was a struggle to reach even single digits, depending on what ports are actually used) --- and more importantly, it comes at the cost of using up main CPU cycles. Cycles which are much better spent doing the rendering on the CPU which is actually equipped for it.

Quote:

Wouldn't it be possible to fragment the scene description as well?

Only to an inconsequential degree. The whole point of tracing the view rays, through reflections and refractions, is that you don't know beforehand where it will end up. If you knew that, you wouldn't need to trace anymore. But if you don't know, you don't know which part of the scene description you will need, and thus which parts you must have available (and which ones you can leave out).

Quote:

As for what's on the board, isn't the Xorro slot supposed to accept additional cores? I don't see why they couldn't use 2nd G chips as well there.

Once you consider adding extra hardware, you might as well say "what about using GpGPU on a PCIe graphics card?". Or "how about hooking up an i7 CPU to the Xorro bus?".

But more importantly, once you consider adding extra hardware, you must consider the cost/benefit ratio of such extra hardware. So if we assume, for the sake of the argument, that XMOS is going to bring out a 2nd gen XCore chip, and that such a chip has an FPU, and some way of attaching memory (rather brave assumptions...) --- then someone would need to create a "Xorro card" with such chips on it. Now, seeing how the X1000 is already a low volume product, such a hypothetical X1000 Xcore Extender is, necessarily, an even lower volume product. It's not like there are hundreds of AmigaOS users desperate to speed up their 3D rendering (see the "What have we done with Blender" thread).
Thus such a board would have to spread its R&D cost over few units, making each of them expensive. So even if you, for some bizarre reason, have a desire to do some of your rendering on something other than a real, grunty CPU or a GPU --- you'd probably still be better off getting a SheevaPlug or PogoPlug for $99, or a BeagleBoard for $149, and just hook them up via ethernet.

@Hyperionmp

Quote:

I wouldn't take his opinion on the XMOS chip very seriously.

No offense but from a technical perspective I would take Umisef's opinion over your's when it comes to the uses of the xmos chip.

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@umisef
Thanks for your detailed replies.

Your suggestion about using GP-GPU or an i7 on Xorro, reminded me of one particular development:

http://www.vizworld.com/2009/09/caustics_3dsmax_demonstration/

The software engineers from SplutterFish (of Brazil R/S fame) in the linked video, explain that GPUs are not that "hot" for real GI (when no pre-baking occurs) and they now teamed up with caustics which produce a card that takes care of "a part" (not all) of their rendering algorithm, resulting in pseudo real time global illumination.
It would seem that both the CPU (obviously) and the GPU are used in some sort of "trio" solution.

If you consider they have that additional i7 in Dual Xeon workstations (nehalem Xeons) why the need of such specialized HW? And why the GPU is not sufficient(?)

Couldn't a cluster of 2G Xmos processors act like the caustic card in prepping that data (not doing everything but just a part)? In the end a 256 Xmos cluster today costs less than that card, and another advantage would be the fact that buying an XMP dev board for testing is very cheap compared to the R&D caustics went through (even Individual Computer could buy one to tinker around...).

All ideas that could be exploited in an eventual X2000 anyway, but that software wise (for how ineffective they might be at the moment) can be studied on the X1000 as well (as I said the latter is a developer's gymn more than enything else).

Last edited by DAX on 26-Jun-2010 at 10:26 PM.

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