@megol

And count the years the Natami was in development, Tina is in some early stage.

@wawa

That sounds like the sanest solution to me as well, only thing is that I'd choose ARM rather than MIPS. I've been playing around with ARM recently (raspberry pi) and it's a very nice architecture, and there are a lot of developers familiar with it - it's the CPU in all iPhones, iPads and most Android devices (although Android is mostly java). MIPS used to be very popular a few years ago, eg in graphics workstations and there was even a port of Windows NT for it, but these days it's used mostly for internet appliances so fewer people are familiar with it.

@CodeSmith

and why not x86?
There are plenty cheap x86s CPUs, there's JIT already developed. Seems like a waste to go MIPS, even ARM.

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@CodeSmith

the thing is that jens is familiar with mips and apparently sees technical advantages in this architecture, even though what i have seen since few years there isnt much going on in the core development.

http://www.a1k.org/forum/showthread.php?t=38998&page=2
post#36

the major factor is performance per buck, i think this is understandable without translation:

Quote:

Das ist eine wirtschaftliche Überlegung: Man kann einen 600MHz MIPS mit Peripherie on-Chip (GBit MAC und USB high speed Host) mit Startup-Flash, 128MByte DDR2-Ram und den notwendigen DC-DC Wandlern für unter 20,- EUR Materialkosten bauen. Das ist ne Menge CPU-Wumms für wenig Geld.

@pavlor

Quote:

Who will write that JIT?

i recall somehow jens meant toni, but i dont know where i have it from, i cant find such a quote. so i would prefer not to put it as a statement, not to be wrong again when i ve prominently wrongly recalled lesters statement to be one of mason;)

i could ask toni directly being in almost daily contact, but then everybody can, and i trust whatever answer was jens would be able to motivate him if he wanted.

@bennymee

Quote:

And count the years the Natami was in development, Tina is in some early stage.

Depends how much time the respective developers have to dedicate to the projects.

@wawa

Quote:

i could ask toni directly being in almost daily contact, but then everybody can, and i trust whatever answer was jens would be able to motivate him if he wanted.

It will be no easy task. Eg. relatively slow progress of E-UAE JIT for PowerPC - and its author knows what to do, he wrote 68k-PPC JIT before (Petunia).

@pavlor

hard to find anyone who knows amiga better than toni wilen..

@wawa

Quote:

hard to find anyone who knows amiga better than toni wilen..

But you need someone who knows good BOTH Amiga AND target CPU architecture.

@WolfToTheMoon

I'd prefer an ARM JIT too. My reasoning would be the millions of cheap ARM devices, including one million Raspberry Pis alone. x86 can be cheap, but it's not as cheap as a $25-$35 computer.

Back in an accelerator thread I brought up an idea of pairing the Pi up with a cheap FPGA board (think it's around $40 or so) ... and putting the Amiga chipset in the FPGAs, and using ARM JIT for the 68K stuff. I think in theory it could work, except for no ARM JIT existing, of course. Anyway, an ARM JIT would at least open up the possibility of lots of speedy emulators on the gazillion ARM devices out there.

Last edited by Nameless on 19-Jul-2013 at 07:26 PM.

@Nameless

Btw, Arrow are selling something they call the SoCKit here, think it's about 250 EUR. The SoC in question is a dual-core 800MHz ARM paired with an FPGA. Both parts have dedicated IO pins plus a few thousand interconnects between them. Unfortunately it's just too low spec CPU with too low spec FPGA at a too high cost to be worth it.

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@olegil

What I was looking at was more in the super-cheap range.

Something like a $35 pi + pixi 200 board. The A model will go for £30.

http://www.astro-designs.com/pixi-200.php

But... I think the FPGA isn't big enough to hold the entire chipset (minus CPU). Maybe AGA could be squeezed in though? I read a bit more on it, and I think it'd need another chip to handle memory retention, or something like that ... but I'm a FPGA newbie, so don't know how those things work. Or how many gates would be even needed.

It was just an idea on how to get a bit more oomph into Pis running Amiga stuff, while at the same time making a super cheap Amiga-like system... or at least a sub $100 system. Still requires that ARM JIT which doesn't exist, so it's all sort of moot.

Last edited by Nameless on 19-Jul-2013 at 08:47 PM.

@WolfToTheMoon

Quote:

WolfToTheMoon wrote: @CodeSmith and why not x86?

Technologically? no reason not to. The chips are cheap, well understood, widely available and powerful. Psychologically?

@wawa

Quote:

wawa wrote: @CodeSmith the thing is that jens is familiar with mips and apparently sees technical advantages in this architecture

Ah, I thought that might be the case. The MIPS architecture is quite nice, and if Jens has worked with it before then that's one less set of unknowns to deal with.

@CodeSmith
jens designed an apparently successful device called nequester:
http://www.jschoenfeld.com/products/nequester.htm
which is based on mips.
except being able to rely on professional experience with the architecture jens had
on multiple occasions mentioned the stability. i cannot judge his statements but he repeatedly accused ppc as being potentially unstable and therefore unreliable in a long run. this opinion comes apparently from his experience with ppc cpus while designing nequester afair.

@wawa

Quote:

ppc as being potentially unstable and therefore unreliable in a long run

Building computers that endure 100 years?

@pavlor

as i said, i only repeat what ive heard of him. he considers ppc unreliable. perhaps its other (industrial) standards he is judging by, where devices need to be completely dependable 24/7 and therefore it has not affected the currently discontinued desktop solutions (while it must have affected ppc servers?). i have no idea..

@WolfToTheMoon

That's true but if we are going that way why not just use UAE? A custom emulator design would provide faster CPU speed but have less compatibility with some software (on the chipset side).

Another option would be to do a 100% FPGA design but still emulate the 68k processor. By going with a customized VLIW it should be possible to do a superscalar processor at ~400MHz* in a Xilinx Kintex 7. As it can be customized for executing translated 68k code the performance can be higher than the frequency indicates.

(* a more than 400MHz simple scalar processor is possible in a Virtex 5 (high end), the Xilinx 7 series is two generations newer and the Kintex 7 (middle end) should be faster than a Virtex 5)

Last edited by megol on 27-Jul-2013 at 12:37 PM.

@megol

Quote:

Highly than the frequency indicates.

I highly doubt that, unless you provide a lot of L3, L2 and L1 cache, and implement out of order execution, branch perdition, and a bunch more complicated optimizations, and a vector unit like VMX.

I really do not think any hobbies can compete whit any company, at producing high end chips, doing a old Z80 or 68000 chip in FPGA is one thing, but doing a modern chip in FPGA is going to be simply to hard to do.

Besides 300 Mhz was difference is going to make? What are going to use a so slow computer for? We are speaking 1997 technology here.
And so you port PC games from 1997 to Amiga? How long is this going to be acceptable speed, before it's too slow?

Last edited by NutsAboutAmiga on 27-Jul-2013 at 12:58 PM.
Last edited by NutsAboutAmiga on 27-Jul-2013 at 12:53 PM.

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@NutsAboutAmiga
Large caches would be needed (probably in a 4kiB (L1 data) - 32kiB (L2 data)- 512kiB (L3 shared) design), branch prediction is of course required but doing an OoO VLIW is hard and would probably make the frequency much lower.

Of course one can't compete with a high performance processor in normal tasks, that's impossible. However if the high performance processor then have to emulate another processor the differences may not be as large. Even with a JiT each executed instruction requires several cycles in practice as translation takes time and some things can be complicated (e.g. branches).

The VLIW design would be simpler than a pure 68k design but still have hardware making interpretation and JiT translation easier. Examples:

. 68k decoding hardware - simple instructions is handled in hardware (translated to VLIW bundles) while complicated is done in software.
. checkpoint/restore mechanism for the register file makes speculative execution easier.
. branch mapping hardware translates indirect 68k branches to VLIW branches.
. trace mapping hardware (also a kind of branch map).
. full conditon code support, each register is extended with a flag word.
. valid bit per register. Allows speculative execution.
. pending bit per register. Another speculation help.
. pointer following code detector (wild idea). This could speed up AmigaOS as it uses linked lists.

I still don't think it could compete with even a middle class Intel i5 but for people that don't want PPC, ARM or x86 it could be an alternative. It should be several times faster than a 68060 anyway. :)