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PosterThread
Fl@sh 
Re: Some Power related news
Posted on 1-May-2021 23:03:31
#401 ]
Regular Member
Joined: 6-Oct-2004
Posts: 215
From: Napoli - Italy

@NutsAboutAmiga

On gcc fsel instruction is enabled by apposite switch.
Not all ppc supports it, if I remember well all embedded cores are ok with this powerful instruction.
The same instruction instead is present on all AltiVec units but is referred to vectors.

I agree with you, to innovate you have to change.
So please, not related to you, don’t use old 68k cpu always as a good example, it made history but design isn’t more actual and have a lot of incongruences and limits.
Consider as example that same code is often incompatible among all models from 68000 to 68060 and for me this is unacceptable.
Especially comparing it with all x86 cpu flavors where compatibility is much more robust.

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NutsAboutAmiga 
Re: Some Power related news
Posted on 2-May-2021 9:08:17
#402 ]
Elite Member
Joined: 9-Jun-2004
Posts: 11649
From: Norway

@Fl@sh

Quote:
The same instruction instead is present on all AltiVec units but is referred to vectors.


but not all PowerPC has AltiVec, load/store is 128bit, max load/store for integer is 32bit (on 32bit PowerPC), and max load/store for float/doubles is 64bit.

When working on arrays I find 128bit to be too large, and 32bit to be too small, ideal size in some cases is 64bit, but doubles can’t be used in binary operations. Yes, I know integer registers are 64bit, but as long as it has to load it in as 32bit, it does not really help.

On the 68000 they had the foresight to include “move.l” despite the data bus only being 16bit, (and Address bus being only 24bit) so the code actually run faster on 32bit bus.

The idea behind 64bit PowerPC isa, is that you don’t need to have new instructions for 64bit as many of the instruction can simply be upgraded to support 64bit internally, so in a sense they reuse transistor logical, to save heat and power. And that’s way they are/where so popular in embedded stuff, I guess.

I have not really messed around in 64bit OS, seen some exsamples shifting in multiple values in register, it can also be that compiler is bit stupid, think about 64bit and 32bit as two different things, when most PowerPC CPU hybrid CPU’s, maybe we are not getting optimal code.

Last edited by NutsAboutAmiga on 02-May-2021 at 11:27 AM.
Last edited by NutsAboutAmiga on 02-May-2021 at 11:27 AM.
Last edited by NutsAboutAmiga on 02-May-2021 at 11:26 AM.
Last edited by NutsAboutAmiga on 02-May-2021 at 10:45 AM.
Last edited by NutsAboutAmiga on 02-May-2021 at 10:44 AM.

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Fl@sh 
Re: Some Power related news
Posted on 2-May-2021 12:37:12
#403 ]
Regular Member
Joined: 6-Oct-2004
Posts: 215
From: Napoli - Italy

@NutsAboutAmiga

You have to go with AltiVec, in integer datatype you can do all you need at max speed, the main difficulty I have encountered was how to control data flow without loose speed. Once you understand how to control it you have win and will get at least 3x performance against scalars.
I suggest you, if you want avoid asm, to go by C intrinsic functions, the code generated should be the same as asm.
In floats it’s limited to float32 datatype in old cpus.

If you don’t want to use AltiVec you have to go with normal cpu registers where of course all depends by implementations so on a 32bit os/cpu you’ll have 32bit access to memory.
On x86 there were some tricks to access to 64bit data’s also on 32 bit systems masking access and resulting in a sort of burst mode. I can be in error but this was introduced on intel Pentium 4 cpus.

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Hammer 
Re: Some Power related news
Posted on 3-May-2021 13:09:48
#404 ]
Elite Member
Joined: 9-Mar-2003
Posts: 4116
From: Australia

@matthey

Quote:

matthey wrote:
billt Quote:

And Risc-V is putting some dents in ARM's marketshare. The Nvidia thing brings some question marks into the ARM universe as well. Any fracturing of the ARM situation can be an opportunity. I think that if the Nvidia buyout does complete, then that would be a good thing for Power.


Assuming the Nvidia buyout of ARM opens up opportunities in the market, isn't POWER in a different market? The Libre project is one research project using POWER for embedded hardware with some weird extensions like a variable length encoding for CPU/GPU vector processors. At least RISC-V is focused on the embedded market and uses a variable length encoding to try to improve code density. POWER/PPC fans will likely say that code density doesn't matter but it has been the ISAs with the best code density which have dominated the embedded market starting with the 68k.

68k baseline
Thumb2 +2% code size
SuperH +16% code size
x86-64 +31% code size
RISCV64IMC +34% code size
AArch64 +50% code size
PPC +81% code size
MIPS +85% code size
SPARC +93% code size

Is it a coincident that the 68k, SuperH and then ARM Thumb2 cores were the best selling 32 bit cores in the embedded market? Can we see why Motorola lost the embedded market when they stopped developing the 68k and forced PPC into the embedded market? Do you still think POWER/PPC has an opportunity in the embedded market because of Nvidia buying ARM? Can we see that RISC-V would have an opportunity because of lack of code density competition?

Why compare 32bit 68K with 64-bit X86 when there's 32-bit X86?

For code density, from http://web.eece.maine.edu/~vweaver/papers/iccd09/ll_document.pdf refer to page 2
For Linux_Logo benchmark, 8086 has superior code density when compared to 68K

For LZSS decompression code,
X86-64 beats SH3
X86-64 beats Thumb-2

For size of string concatenation code
X86-64 beats SH3
X86-64 beats Thumb-2

For size of string searching code
X86-64 beats SH3
X86-64 beats Thumb-2


For size of integer printing code
X86-64 beats SH3
X86-64 beats Thumb-2


I'm game for another ISA debate?

Last edited by Hammer on 03-May-2021 at 01:14 PM.
Last edited by Hammer on 03-May-2021 at 01:10 PM.

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matthey 
Re: Some Power related news
Posted on 4-May-2021 1:43:53
#405 ]
Cult Member
Joined: 14-Mar-2007
Posts: 888
From: Kansas

Hammer Quote:

Why compare 32bit 68K with 64-bit X86 when there's 32-bit X86?


I almost added x86 which is a few percent better than x86-64 but x86-64 is much more popular now. I also already had AArch64 which is 64 bit so it didn't seem out of place.

Hammer Quote:

For code density, from http://web.eece.maine.edu/~vweaver/papers/iccd09/ll_document.pdf refer to page 2
For Linux_Logo benchmark, 8086 has superior code density when compared to 68K


The 8086 program runs on MS DOS and has no header overhead. The competition requires the program to run on Linux. At the top of the page is the text, "31 Architectures, Smallest Linux executable is 870 bytes! (on m68k)". Out of 31 architectures, the 68k has the smallest Linux executable. The 8086 would likely win the contest if Linux supported the 8086. The contest program is small and does a lot of byte processing which the 8086 is excellent at.

Hammer Quote:

For LZSS decompression code,
X86-64 beats SH3
X86-64 beats Thumb-2

For size of string concatenation code
X86-64 beats SH3
X86-64 beats Thumb-2

For size of string searching code
X86-64 beats SH3
X86-64 beats Thumb-2

For size of integer printing code
X86-64 beats SH3
X86-64 beats Thumb-2


x86-64 code is compact for some algorithms. These examples were optimized for size which sometimes causes a large instruction count increase for x86-64 likely decreased performance. When optimizing for performance, x86-64 instruction counts drop but code density suffers. The 68k maintains low instructions counts and good code density whether optimizing for performance or size. SH-3 code density is worse than advertised and it always suffers from high instruction counts, often worse than x86-64. Thumb 2 looks to me like a superior ISA to SH-3. It requires more instructions than the original ARM encoding but not excessively considering the good code density and simpler decoding than CISC ISAs require. Where x86-64 beats Thumb2 in code density it is not by much and I would expect Thumb2 to have better code density overall, especially when optimizing for performance.

Hammer Quote:

I'm game for another ISA debate?


It would probably be better to move any code density debate to "The (Microprocessors) Code Density Hangout" thread. POWER/PPC and code density usually aren't mentioned together.

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simplex 
Re: Some Power related news
Posted on 4-May-2021 2:24:56
#406 ]
Cult Member
Joined: 5-Oct-2003
Posts: 840
From: Hattiesburg, MS

@matthey

Quote:
The 8086 would likely win the contest if Linux supported the 8086. The contest program is small and does a lot of byte processing which the 8086 is excellent at.

I know almost nothing about this, but I noticed that they author had mentioned 8086 was an 8/16 bit architecture, while 68k and many others were 32 bit. Could that be a contributing cause?

(I realize not all the 8-bit architectures had better code density, but I was wondering how a 6809 would do.)

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Hammer 
Re: Some Power related news
Posted on 6-May-2021 14:02:15
#407 ]
Elite Member
Joined: 9-Mar-2003
Posts: 4116
From: Australia

@matthey

Quote:

I almost added x86 which is a few percent better than x86-64 but x86-64 is much more popular now. I also already had AArch64 which is 64 bit so it didn't seem out of place.

68K is a 32bit CPU with 32-bit address space for 68020-to-68060, hence the apples to apple comparison should be i386.

X86-64 is used for high-end desktop and large server apps. x86-64 didn't remove IA-32 modes. X86-64 includes mandatory SSE2 SIMD which is missing on 68K.

Quote:

The 8086 program runs on MS DOS and has no header overhead. The competition requires the program to run on Linux. At the top of the page is the text, "31 Architectures, Smallest Linux executable is 870 bytes! (on m68k)". Out of 31 architectures, the 68k has the smallest Linux executable. The 8086 would likely win the contest if Linux supported the 8086. The contest program is small and does a lot of byte processing which the 8086 is excellent at.

For Linux logo, i386 is under 1024 bytes.

Linux-8086 is a subset of 32bit Linux. https://en.wikipedia.org/wiki/Embeddable_Linux_Kernel_Subset



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