https://www.eetimes.com/document.asp?doc_id=1334087
mips cpu goes open source

@hardwaretech
Good article. MIPS appears to be feeling the competition from RISC-V and has reason to worry. MIPS used to be one of the classic pure and simple RISC ISAs but the ISA has been changed as much as the ownership. It is now more modern and has similarities to RISC-V although RISC-V is now simpler than MIPSr6 for the RISC purists. RISC-V has less ISA baggage and more encoding space for customization while MIPS CPUs can often use safer expired patents and the ISAs and tools are more mature. RISC-V has done a better job of marketing code density but it looks like MIPS has made improvements also. While MIPS16 and microMIPS compressed encodings were unimpressive, the new nanoMIPS does appear to be closer to Thumb2 in some cases.

"The company tested the new [nanoMIPS] ISA using the CSiBe code-size benchmark, developed by the University of Szeged (Hungary), for the GCC compiler. On those tests, nanoMIPS compresses by approximately 15% programs that contain the most frequently used MIPS16e2 instructions. Performance-optimized MIPS32 code receives a 35% reduction."

http://www.linleygroup.com/newsletters/newsletter_detail.php?num=5857&year=2018&tag=3

MIPS has a poor reputation for code density while ARM has a good reputation but nanoMIPS likely beats AArch64 in code density. ARM deprecated Thumb2 choosing a more standardized, performance oriented and robust (fat) but less dense AArch64. Customization, code density and efficiency were the selling points of ARM but they have made a big gamble moving away from their strengths. At least they are offering products different from the competition. RISC-V and MIPS are fighting for similar embedded markets. RISC-V appears to be winning the marketing battle but MIPS has strong support in China and being more open is likely to improve adoption.

@hardwaretech

I wonder if anyone could produce upclocked R16k cpu boards for all the old SGI kit out there... doubt there’d be a market for it now, but it’d be cool to see.

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@matthey

ARM deprecated Thumb2? What about embedded and Cortex-M, are they giving up that market?

Quote:

hth313 wrote: ARM deprecated Thumb2? What about embedded and Cortex-M, are they giving up that market?

It is not entirely clear to me what ARM is doing. ARMv8 does deprecate some parts of Thumb encodings even though it allows for them too (compilers give deprecation warnings for IT blocks). ARMv8 includes AArch32 but it requires the VFP and NEON SIMD units (too big for the Cortex-M). The existing Cortex-M ARMv7 designs which use Thumb encodings will be around for some time but I don't know what ARM will do after that. Maybe they will continue to use the old ARMv7 designs as updating them to ARMv8 AArch32 makes no sense. Usually, older ARM versions are discontinued (like ARMv6 and older today).

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0801b/IBAIEGDJ.html

Last edited by matthey on 19-Dec-2018 at 05:12 PM.
Last edited by matthey on 18-Dec-2018 at 11:07 PM.

@hardwaretech

I was happy to see this. I learned MIPS assembly in school using the Hennessy book, so I've got sort of a soft spot for it, even if does just slowly fade away.

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so i wanna know how fare out in the future are the optical/laser light based cpu's ???..
i saw a video about a laser light based optical cpu accalrator pci-e card but nothing ever came out of it ? you cant buy them anywere.. do any one think it will be posible to put in an pci-e cpu accelrator card in side some of the new comming amiga one's. if there will fix the smp cpu issue ??

Quote:

bison wrote: I was happy to see this. I learned MIPS assembly in school using the Hennessy book, so I've got sort of a soft spot for it, even if does just slowly fade away.

My only assembly programming in school (college) was 68000 programming on an Atari ST. The 68k was terminated in its prime (most popular embedded 32 bit CPUs in the world) instead of slowly fading away. Its PPC replacement slowly faded away to ISAs with inferior code density to the 68k. After the parent company faded away to China (Motorola) and the Netherlands (Freescale), Freescale/NXP now pays licensing fees to the 68k replacement as the most popular embedded 32 bit CPUs in the world. The biggest competitor to the 68k went on to make the most powerful desktop CPUs today even though its ISA was generally considered inferior. Yet, the 68k gets little respect today. RISC has become more CISC like with variable length instructions for better code density, more powerful addressing modes, load/store multiple instructions, large instruction sets and more complex instructions yet the "pure" RISC MIPS survived and the 68k died. Ironic and sad but somehow appropriate for the Amiga which was at one time superior to the competition but is on the verge of extinction today.

@thread

MIPS now switches to RISC V.

liliputing url
Quote:

MIPS Technologies, the company that had been synonymous with the MIPS processor architecture, is now shifting its business model. Instead of designing MIPS chips, the company will be developing processors based on RISC-V architecture.

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Risc V uses some of the designs of the old MIPS chip because one of the designers of the Mips now works for RISC V. From what I understand current RISC v is faster than the arm in the pie. A RISC V board is now on sale for $125.

Last edited by hardwaretech on 09-Mar-2021 at 05:38 PM.

update -read more-https://www.tomshardware.com/news/mips-changes-business-model-risc-v

Last edited by hardwaretech on 11-Mar-2021 at 03:01 AM.

@hardwaretech

And this board for $660 https://abopen.com/news/a-look-at-the-risc-v-pc-from-sifive/

How compatible is this to the PowerPC world ?

from-
https://www.reddit.com/r/RISCV/comments/e1t5lt/riscv_compared_to_powerpc_risc_isa/

RISC-V is much more similar to PowerPC than it is to ARM. The major technical differences are that PowerPC has condition codes (in fact eight sets of them -- very unique!), PowerPC has dedicated Link Register and Loop Counter registers logically in a functional unit with the Program Counter, and PowerPC is strictly fixed-length 32 bit opcodes while RISC-V gets better code density by mixing 16 bit and 32 bit opcodes. PowerPC did a very good job of planning for having both 32 bit and 64 bit processors.

PowerPC has sometimes been criticized as "not really being RISC" because of its large number of instructions. I've never agreed with that argument. It's RISC if each individual instruction is RISC, the total number of instructions is irrelevant.

PowerPC has two features that are not as pure-RISC as RISC-V. First there is a restricted kind of load and store multiple that can transfer data between a block of memory all all the registers from register N up to register 31. It's pretty easy to have, for example, the instruction decoder just expand this into a series of loads and stores in the pipeline. Other RISCs, such as ARM, have more complex versions of this. The other thing is load instructions with writeback of the calculated address to the base register. This makes these instructions produce two results, which is a little bit unRISCy. However, those results are available at different times (the writeback can happen immediately as the "normal" result while the load arrives who knows when, depending on cache hit or miss etc. Again plenty of other "RISC" ISAs have similar instructions.