It appears that the cost of designing custom ASICs may be coming down soon:

https://www.sifive.com/chip-designer

"
01. Design

Choose the base SoC that suits your application. Create variations using a rich library of IP from our DesignShare Partners — or onboard your own IP. Save as many custom SoC designs as you like.

02. Prototype

Run your application code on virtualized chips. Iterate until you get the performance that’s right for your product.

03. Order

Receive sample chips within weeks — at a deep discount. With SiFive, there are no upfront IP costs until you need production quantities.
"

"Freedom Everywhere

Designed for embedded microcontrollers, IoT, wearables, and more.

TSMC 180nm process"

"Freedom Unleashed

Unix-capable SoCs suitable for machine learning, storage, networking, and more.

TSMC 28nm process"

I would suggest there are a few things to note here.

Firstly "onboard your own IP" can mean new 68k CPU designs as well as custom Amiga chipset designs, there's no need to stick with RISC-V.

Secondly "there are no upfront IP costs until you need production quantities" means that the cost to get started should be drastically reduced.

Thirdly, the option to choose between a 180nm process (formerly used in the Pentium 3: https://en.wikipedia.org/wiki/180_nanometer ) and a 28nm process (a process node that's smaller than what was used for Intel CoreSandy Bridge CPUs: https://en.wikipedia.org/wiki/Sandy_Bridge) means that there's the potential to start with a cheaper process technology and ramp up to something that could bring classic Amiga hardware into the 21st century.

Whilst this seems like a good opportunity, it's still a considerable technical challenge to design ASICs, so I don't want to downplay how hard it'll be to take advantage of this, but I would say that it is something to be aware of for the Vampire and Minimig-variants.

Any thoughts?

@HenryCase

I do not know much of these matters, but my thinking is that if embedded companies are not interested in a new 68k, then maybe one can approach either NXP and see if they are interested in licensing out the old design? The alternative is the Vampire core.

Regarding Amiga chip sets, would it be possible to base it on the existing Commodore design? Maybe Cloanto owns that now too. I mean, it is so old I do not really see a point to improve it, just use it as is for the best compatibility. For a more modern alternative/complement, there are alternative GPUs on the market today that maybe can be used in addition.

Some interested people can perhaps form a kickstarter or similar. Maybe there are some ex-Commodore people that are interested. The resurrected Sinclair Spectrum brought in people from the old days if I understand it right.

Anyone, please make a standard motherboard so we can put together new (old) Amiga computers from off the shelf parts.

@HenryCase

Thanks for sharing.
This is very interesting.
I guess new OCS chips are a candidate.

_________________
John 3:16

@hth313

Quote:

I do not know much of these matters, but my thinking is that if embedded companies are not interested in a new 68k, then maybe one can approach either NXP and see if they are interested in licensing out the old design? The alternative is the Vampire core.

I had envisioned this being a project undertaken by the Amiga community (relying on Vampire and Minimig-based designs), but if NXP are interested in licensing their 68k CPU designs at prices that hobbyists can afford then sure why not! I'll not be asking them myself, but anyone that fancies trying is welcome to do so.

Quote:

Regarding Amiga chip sets, would it be possible to base it on the existing Commodore design? Maybe Cloanto owns that now too. I mean, it is so old I do not really see a point to improve it, just use it as is for the best compatibility. For a more modern alternative/complement, there are alternative GPUs on the market today that maybe can be used in addition.

Again, I'd rather not involve other companies, but if someone wants to ask them then be my guest. We can take existing AGA implementations from the Minimig (and variants) as a starting point.

Quote:

Some interested people can perhaps form a kickstarter or similar. Maybe there are some ex-Commodore people that are interested. The resurrected Sinclair Spectrum brought in people from the old days if I understand it right.

A Kickstarter makes sense at a later stage, but at this moment in time there would still need to be work done to design the ASIC. Perhaps someone with the skills to do this work could start a Patreon account (or something similar) during the initial investigation phase.

Quote:

Anyone, please make a standard motherboard so we can put together new (old) Amiga computers from off the shelf parts.

That's also a possibility I hadn't considered, as I had envisioned a SoC (System-on-Chip) design where the 68k CPU, RAM and Amiga chipset were integrated into a single chip. However, you raise a good point by bringing this up, as it would be possible to design pin-compatible (and voltage-compatible) replacements for original Amiga chips that could then replace those on the original motherboards (or on new motherboard designs). This could be an attractive option to Amiga enthusiasts.

Regarding someone making a new standard Amiga motherboard, I believe there have been a number of attempts of doing this. For example, one of the most recent examples is the Re-Amiga 1200 by Chucky:

http://wordpress.hertell.nu/?p=587

https://www.youtube.com/watch?v=jMg3h2Kz1_A

It'd be good if we could add a couple of extra features (such as on-board HDMI output) but in general I don't think the motherboard is going to be an issue in a classic Amiga revival project.

@Trekiej

Quote:

I guess new OCS chips are a candidate.

I would say any FPGA Amiga is a good candidate. For example, the Minimig MiSTer supports OCS, ECS and AGA and is open source:

https://github.com/MiSTer-devel/Minimig-AGA_MiSTer

There are two general approaches taken to moving from an FPGA to an ASIC. One is to target a Structured ASIC design, which (from what I understand) simplifies the ASIC routing process by providing starting blocks that are closer in design to an FPGA, at the cost of some performance. The second approach is to design a custom ASIC, which is a harder challenge but one where you have a lot more opportunity to tune the design for greater performance.

Assuming for a second that there's a desire to go down the custom ASIC route, to get an idea of what this process looks like, take a look at the summary provided in this Quora answer:

https://www.quora.com/How-do-you-convert-a-design-in-FPGA-to-an-ASIC-What-are-some-companies-that-will-do-such-a-conversion-for-you-and-what-do-they-need-from-you/answer/Evgeni-Stavinov

Quote:

Here is a very top-level list of FPGA-to-ASIC conversion steps: * Identify the fab (link) * Identify specific ASIC standard cell library to be used * Identify synthesis and place&route tool (Synopsys, Cadence, etc.) * Port all FPGA-specific cores to ASIC: RAMs, DSPs, IOs, transceivers, other FPGA-specific IP cores (PCIe, etc.) * Design verification using functional simulation and other methods * Get the design thru synthesis and place & route * Pass all DRCs * Tape-out

Another of the answers to the same Quora question provided a link to a set of open source tools for performing ASIC design work:

https://www.quora.com/How-do-you-convert-a-design-in-FPGA-to-an-ASIC-What-are-some-companies-that-will-do-such-a-conversion-for-you-and-what-do-they-need-from-you/answer/Rob-Anderson-104

http://opencircuitdesign.com/

It may be best to wait until the SiFive Chip Designer software is released before commencing with this work, but exploring the existing design tools should help build an understanding of how to go from an FPGA design to an ASIC.

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@HenryCase: SiFive is a company co-founded by one of the RISC-V designer. And AFAIR they use Chisel (instead of VHDL or Verilog): https://chisel.eecs.berkeley.edu

@cdimauro

Thanks for the link. As far as I know, HDL languages like Chisel, VHDL, Verilog, etc... are used in FPGA design, but aren't used in ASIC design.

In ASIC design you need to design the physical layout of the gates, rather than just describing their function. With that in mind, Chisel is useful for prototyping cores on FPGAs, but another set of tools is required to turn those designs into ASICs.

This video course gives an quick overview of how ASICs are designed (if you want to jump straight to the design workflow part of the course, that starts in Episode 11):

https://www.youtube.com/watch?v=pvhWzOE2CYk&list=PLA18F9B9E9316050E

Last edited by HenryCase on 16-Mar-2019 at 03:08 PM.

@HenryCase

I doubt NXP will be interested in a new 68k, too little money for them to bother, but it would not harm to ask and who knows. At least it can be a polite thing to do as they own the original design.

I was more thinking of the Amiga chipset as a single chip design. The alternative is a SoC with a 68k. But yes, one could of course remake the chipset as it was, but that is perhaps not cost efficient. RAM is usually placed outside, only caches are on chip?

With the Amiga motherboard I mean a 68k coupled with a single-chip Amiga custom chip replacement and then add various off-the-shelf components. Something like a 68k alternative to Tabor/X5000. This could also be turned into an A1200, but that is more complicated as it requires more specialized manufacture, with keyboard and case components.

Maybe a RPi style thing is more appropriate, I cannot tell. Anyone who dives into it will probably figure out the best way.

Regarding my idea of finding people, there are lots of competence around here and there, perhaps even some old love from some of the original engineers. Many are coming to age and are maybe not chasing a career as much anymore.

Producing hardware is so over my head.

@hth313

Quote:

I doubt NXP will be interested in a new 68k, too little money for them to bother, but it would not harm to ask and who knows. At least it can be a polite thing to do as they own the original design.

As suggested before, I'm not opposed to that idea, I'm just not going to be the one to do it (I've asked for access to hardware designs from Amiga hardware manufacturers in the past, it's not an experience I want to repeat, but perhaps someone else will have more luck).

Quote:

I was more thinking of the Amiga chipset as a single chip design. The alternative is a SoC with a 68k. But yes, one could of course remake the chipset as it was, but that is perhaps not cost efficient. RAM is usually placed outside, only caches are on chip?

The issue with just producing a new Amiga chipset ASIC (and using an existing 68k CPU to go along with it) is that there's likely to be a massive mismatch in power. Bear in mind the approach we're talking about will get us well into the GHz range of processor clock speeds. I don't think a 100Mhz 68060 and a 2GHz AGA chipset would be a good match.

There are existing open source 68k CPU implementations designed for FPGAs that we could use as a starting point, so we don't have to start from scratch. I believe that the Vampire team have also suggested in the past they'd be open to licensing the 68080 design, so collaboration with them may be another option.

Regarding RAM on a SoC, there are a couple of options here. The most commonly used option is a "Package on Package" design ( https://en.wikipedia.org/wiki/Package_on_package ) where the RAM is stacked on top of the CPU. Whilst it could be argued that the CPU and RAM are on separate pieces of silicon (and so not quite a true system on a chip), they're wrapped up in the same package, so from a user's perspective they're basically indistinguishable from a more integrated SoC.

Quote:

With the Amiga motherboard I mean a 68k coupled with a single-chip Amiga custom chip replacement and then add various off-the-shelf components. Something like a 68k alternative to Tabor/X5000. This could also be turned into an A1200, but that is more complicated as it requires more specialized manufacture, with keyboard and case components. Maybe a RPi style thing is more appropriate, I cannot tell. Anyone who dives into it will probably figure out the best way.

Whilst I personally think looking into potential form factors now is a bit like putting the cart before the horse, if there's no desire to produce separate 68k CPU and AGA chips, then I'd suggest one attractive form factor would be to mimic the Raspberry Pi Compute Module design, which is essentially a full computer contained on a motherboard the size of a DDR2 RAM module:

https://www.raspberrypi.org/products/compute-module-3/

The main benefit of this approach is flexibility, as it'd open up a large range of potential uses, including handheld games consoles, laptop computers, HTPCs, etc...

If we made this hypothetical Amiga to be fully/mostly pin compatible with the Raspberry Pi Compute Module we could even make use of some of the existing devices that are designed around it. To give a few examples of the types of projects that have been built to use the Raspberry Pi Compute Module:

Slice HTPC (no longer for sale, but the idea was sound)
https://www.raspberrypi.org/blog/slice-a-media-player-using-the-raspberry-pi-compute-module/

Circuit Sword (enables use of a Compute Module in a Game Boy Zero)
https://www.youtube.com/watch?v=_STKUuXv-eM

Board that converts a Compute Module into a "standard" Raspberry Pi
https://www.instructables.com/id/Design-Your-Own-Raspberry-Pi-Compute-Module-PCB/

Quote:

Regarding my idea of finding people, there are lots of competence around here and there, perhaps even some old love from some of the original engineers. Many are coming to age and are maybe not chasing a career as much anymore. Producing hardware is so over my head.

To make this clear, I'm not against your idea, but I wouldn't want to rely on it. If old hands get involved to lend their expertise, that's great, they'd definitely be more than welcome, but if not then it's just an opportunity for the rest of us to level up our own skills. Even if we don't get such a project finished, there's no doubt it has the potential to be a great learning experience.

With that spirit in mind, I can definitely recommend the book "Code - The Hidden Language of Computer Hardware and Software" by Charles Petzold:

https://www.amazon.co.uk/Code-Language-Computer-Hardware-Software/dp/0735611319

It's an excellently paced book that goes from the foundational history of digital logic up to the elements of digital logic involved with a computer system. I'd recommend it even as casual reading material regardless of whether someone intended to use the knowledge it imparts or not, as it's interesting (in my opinion) to get a better grasp on how computers work.

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Last edited by HenryCase on 16-Mar-2019 at 08:16 PM.
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I found a few other links related to ASIC design that I figured were worth sharing. At this point in time I'm just trying to build a better picture of the steps involved, as the world of ASIC design is pretty new to me.

"VLSI and ASIC Technology Standard Cell Library Design", a website with existing VLSI/ASIC designs, shared for educational purposes
http://www.vlsitechnology.org/

Baya is an open source tool that assists with building SoCs from smaller components (probably more useful for FPGA designs, but including it here as I thought it was interesting)
http://www.edautils.com/Baya.html

LayoutEditor is a layout tool for ASICs. It's not open source but a free version is available
https://layouteditor.com/

VLSI Academy
http://www.vlsiacademy.org/

If anyone has links related to ASIC design that you want to share, please feel free to do so.

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@HenryCase Quote:

HenryCase wrote: @cdimauro Thanks for the link. As far as I know, HDL languages like Chisel, VHDL, Verilog, etc... are used in FPGA design, but aren't used in ASIC design. In ASIC design you need to design the physical layout of the gates, rather than just describing their function. With that in mind, Chisel is useful for prototyping cores on FPGAs, but another set of tools is required to turn those designs into ASICs. This video course gives an quick overview of how ASICs are designed (if you want to jump straight to the design workflow part of the course, that starts in Episode 11): https://www.youtube.com/watch?v=pvhWzOE2CYk&list=PLA18F9B9E9316050E

I know the differences (albeit I don't work with neither).

Chisel supports both FPGAs and ASICs.

@cdimauro

Quote:

I know the differences (albeit I don't work with neither). Chisel supports both FPGAs and ASICs.

That's news to me. I can't see anything about that on the website (other than "Generates low-level Verilog designed to pass on to standard ASIC or FPGA tools" but that's a standard feature of HDLs, part of the common ASIC design workflow to use HDL tools for prototyping).

Can you point me in the direction of any article that describes how Chisel is used to design ASICs? If it has advanced features for doing this (beyond what common HDLs provide) then it could be a good option.

Last edited by HenryCase on 17-Mar-2019 at 09:49 AM.

@HenryCase: as I said before, I've no experience with FPGAs/ASICs coding neither with Chisel.

I cannot give you direct answers, but I know that Chisel was used to generate the RTL for Berkeley's RISC-V Rocket (an in-order design) and BOOM (an out-of-order design), which were running in the Ghz range. The chips were fabbed by TSMC, AFAIR.

I've no time now, but if you search on YT for both chips, you'll find some nice videos about them, and how Chisel was used to design and produce the final silicon.

Our IP (minimig, apollo, tg68, whatever, would need to be translated or bridged to the TileLink bus that this stuff seems to use. Then, what do we use the RiscV for?

_________________
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@HenryCase

Quote:

HenryCase wrote: @cdimauro Quote: I know the differences (albeit I don't work with neither). Chisel supports both FPGAs and ASICs. That's news to me. I can't see anything about that on the website (other than "Generates low-level Verilog designed to pass on to standard ASIC or FPGA tools" but that's a standard feature of HDLs, part of the common ASIC design workflow to use HDL tools for prototyping).

It's used for design, not only prototyping.

Quote:

Can you point me in the direction of any article that describes how Chisel is used to design ASICs? If it has advanced features for doing this (beyond what common HDLs provide) then it could be a good option.

Why would it need to have some specific feature to work for ASICs? I'm sure it allows instantiation of some part in the standard library and if it doesn't one could insert it in the generated HDL code.

@billt

Quote:

billt wrote: Our IP (minimig, apollo, tg68, whatever, would need to be translated or bridged to the TileLink bus that this stuff seems to use. Then, what do we use the RiscV for?

We don't need to use RISC-V for anything. The platform itself is attractive as it lowers the cost barrier for getting started, and provides access to relatively small process nodes. There are existing options that provide one of those things, but I haven't seen any competing option that supports both (e.g. both 28nm processes and no/low NRE cost for samples). If you know of such an option, please feel free to share it.

@megol

Quote:

It's used for design, not only prototyping.

Depends on what you mean by "design". It's used within the design flow that many ASICs go through, but the bulk of the design work involved in ASIC design is in translating the proposed logic into something that can be manufactured. That's why I referred to the HDL stage as prototyping, as the HDL only provides a description of the functions of the chip, there's a lot of work involved in translating that to an ASIC. Whilst it's technically part of the design workflow, I want to make this distinction so that people don't get the impression that you can just "compile" the HDL in a special way to get an ASIC.

@HenryCase
Of course not just as one doesn't just compile HDL to get an FPGA. There have to be a mapping of the HDL constructs to the physical reality but the HDL is a description of the design and is what is implemented. It's not a prototype just as the C++ sourcecode isn't a prototype of the finished compiled program.

With the appropriate parts library one can in theory just "compile" HDL and get a finished ASIC.

@megol

Quote:

With the appropriate parts library one can in theory just "compile" HDL and get a finished ASIC.

You should tell the semiconductor industry they've been doing it the hard way all these years, I'm sure they'll be pleased to know they don't have to bother employing expensive VLSI design engineers anymore.

HDLs help with describing an ASIC, and with testing/simulation, but as the saying goes, don't mistake the map for the territory.

To give an analogy, imagine you're building a skyscraper. One approach you could take is to have an architect design the building and then employ a bunch of builders to make it a reality. However, doing so is risky, which is why civil engineers get employed, to refine the intended design into something that will be structurally sound, both with reference to the building structure and its place within its environment.

It's similar with ASICs. A HDL description of a chip is the "architect's vision", but there's a lot of work that goes into translating that vision into a the physical structure of a working ASIC. In order to fully automate this process you'd need a lot more than just an "appropriate parts library" (unless you intend to build a "structured ASIC", which is suboptimal compared to a custom ASIC). Bear in mind that in the process of translating a HDL description of a chip to a physical device then the laws of nature will almost certainly get in the way of your idealised vision of how the chip should behave, and those constraints will have to be designed around in order to get a functioning chip, and whilst you could rely on AI-based solutions to mimic how an experienced engineer would tackle these issues, I'd suggest we're not there yet (hence why it's still a lucrative career).

Whilst I respect that the term "prototyping" may have been misleading without further qualification, hopefully we can move past that now and carry on exploring the possibility of a classic Amiga SoC.

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@megol

Quote:

With the appropriate parts library one can in theory just "compile" HDL and get a finished ASIC.

It is quite a lot more complicated than "make chip" and wait for your chips to come back.

In addition to HDL functional and testbench/simulation code, you also need to do a lot of power analysis and design, timing analysis, formal analysis (does the synthesized circuit functionally match your HDL input, or is it somehow different?), Physical implementation rule checks and layout vs schematic matching checks, parasitic cap/resistor extraction and related performance/functional verification, and Design For Manufacturing (DFM) rule checks are now becoming popular as well. Does your IO arrangement suffer from any Simultaneous Switching Noise? (ie. can all IOs change reliably from one value to another in the given clock period, without dropping voltage or current below or above required min/max levels? Run Antenna rule checks, which is a manufacturing issue, not an RF issue. Fail that and manufacturing phenomena at metal layers can destroy your transistors and ruin the chip... Thermal analysis. And correction work for any failures anywhere. This is just what I can think of off top of my head, sorry if I forget anything.

Also, anything optimized for FPGA is not optimized for ASIC, perhaps you may want to improve there, perhaps not... There are some FPGA->ASIC design workflows to help from some foundries.

Last edited by billt on 20-Mar-2019 at 01:03 AM.

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