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      /  Amiga assets: are they now liabilities?
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Poll : Have Amiga's biggest assets become liabilities?
Yes
No
I don't care, I'm just along for the ride.
The relationship is complicated. (Explain)
 
PosterThread
matthey 
Re: Amiga assets: are they now liabilities?
Posted on 20-Jun-2021 18:44:10
#41 ]
Super Member
Joined: 14-Mar-2007
Posts: 1129
From: Kansas

Hammer Quote:

From http://eab.abime.net/showthread.php?p=1491547#post1491547 since you are banned from eab forum


Perhaps this post was meant to be a reply to my post on this forum in the "Back when Ben was the White Knight!" thread?

https://amigaworld.net/modules/newbb/viewtopic.php?mode=viewtopic&topic_id=44218&forum=14&start=20&viewmode=flat&order=0#842836

This does seem like a more appropriate thread for the topic.

Hammer Quote:

PA-7100LC has an extra integer unit and is designed as a low-cost microprocessor for low-end systems.

The first systems to feature the PA-7100LC were introduced in January 1994. These systems used 60 and 80 MHz parts. A 100 MHz part debuted in June 1994

The PA-7100LC was based on the PA-7100. Major improvements were improved superscalar execution and an extra integer unit.

Superscalar execution was improved by adding the extra integer unit and modifying the control logic so that two integer instructions, two load-store units, or an integer and a load-store can be issued in one cycle in addition to the existing instruction combinations supported by the PA-7100

From https://www.wikiwand.com/en/PA-7100LC


The "low end systems" applies to lower end workstations as can be seen below in the wiki where it says, "the PA-7100LC was designed for mid-range multimedia workstations". The two integer units and load store units bring it up to near parity with the 68060 in execution potential but the 68060 has fewer instructions to execute, doesn't have an instruction fetch bottleneck due to horrible code density and has *much* more efficient caches. The PA-7100LC only had 1kiB of on chip instruction cache and no on chip data cache. From RISC-V research, improving code density by 25%-30% is like doubling the ICache size so the 68060 8kiB L1 ICache performance should be better than a 16kiB ICache would be for the PA-7100LC while the PA-7100LC 1kiB L1 ICache performance is closer to that of a 68020.

Hammer Quote:

68060 needs 0.6 micrometre process fab tech with 2,500,000 transistors. 68060 Rev 1 can be overclocked to 63 Mhz on TF1260 with ease.

PA-7100LC needs 0.8 micrometre process fab tech with 900,000 transistors. 1994 PA-7100LC at 0.8 micrometre process fab can reach 100 Mhz.


It doesn't matter how fast the CPU is clocked if it is waiting on instructions and data which it looks like the PA-7100LC would be doing often. The next generation PA-7300LC added on chip 64kiB L1 ICache and 64kiB L1 DCache and the transistor count jumped to 9.2 million transistors (8 million for caches). The area increase would have made this a much more expensive chip back then but the performance jump would have been large. The PA-7300LC should outperform the 68060 using the same die size and at the same clock speed by brute force but I bet the efficient little 68060 would come closer in performance than expected.

Hammer Quote:

Each integer unit can support SIMD32 (2X packed INT16).

PA-7100LC at 100 Mhz would give 1994 Pentium 100 Mhz some heartburn but in 1995, Intel released classic Pentium 200 Mhz and Pentium Pro (up to three instruction issue per cycle, out-of-order processing) 200 Mhz.

0.8 micrometre process fab tech for Pentium 50 to 66.
0.6 micrometre process fab tech for Pentium 75 to 120.
0.35 micrometre process fab tech for Pentium 120 to 200.


PA-RISC was soon left in the dust too. Only Alpha had worse code density than PA-RISC of major RISC ISAs. At least the Alpha designers discovered quickly that the Alpha needed efficient multi-level caching while the PA-RISC designers were obsessed with minimalist cores with inadequate caching. Maybe this wouldn't have been so bad if the designs were for the embedded market but they were for workstations. Even ARM lacked enough performance without caches for most embedded use and only took off when StrongARM added more practical on chip caches. The x86 CPUs started out with inferior caching and an inferior ISA to the 68k CPUs but Intel eventually learned how to make efficient caches given many redesigns fueled by the PC clone market which propelled them past the competition.

Hammer Quote:

Amiga Hombre has extra hardware for texture mapping, Gouraud shading and Z-buffering.


3D hardware could be added to the Amiga chipset too. PA-RISC is not required. The only advantage of PA-RISC was the SIMD unit and it really wasn't that special as it could only do 2x16b integer only operations as planned for the Hombre.

Hammer Quote:

Hombre was to be fabricated in 0.6 micrometre 3-level metal CMOS with the help of Hewlett-Packard.


How sad is it that MOS Technology which started the PC revolution with innovations and a vision to drive down the price of CPUs couldn't use the CMOS process a few years later under CBM control?

Last edited by matthey on 20-Jun-2021 at 07:00 PM.
Last edited by matthey on 20-Jun-2021 at 06:51 PM.

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Hammer 
Re: Amiga assets: are they now liabilities?
Posted on 21-Jun-2021 5:37:01
#42 ]
Elite Member
Joined: 9-Mar-2003
Posts: 4255
From: Australia

@matthey

Quote:

The "low end systems" applies to lower end workstations as can be seen below in the wiki where it says, "the PA-7100LC was designed for mid-range multimedia workstations". The two integer units and load store units bring it up to near parity with the 68060 in execution potential but the 68060 has fewer instructions to execute, doesn't have an instruction fetch bottleneck due to horrible code density and has *much* more efficient caches. The PA-7100LC only had 1kiB of on chip instruction cache and no on chip data cache. From RISC-V research, improving code density by 25%-30% is like doubling the ICache size so the 68060 8kiB L1 ICache performance should be better than a 16kiB ICache would be for the PA-7100LC while the PA-7100LC 1kiB L1 ICache performance is closer to that of a 68020.

PCX-T PA-7100LC has 1KB L1 cache and 2MB L2 cache secondary die.

The proposed Amiga CD64 with PA-RISC @ 0.60-micrometer variant and it's not a workstation e.g. reduced/missing L2 cache.

Amiga Homber's PA-RISC CPU is on-based 0.60-micrometer process tech, hence it could be PA-7200 with a 2 KB L1 cache.

http://www.cpushack.com/PA-RISC.html#2

I'm already aware of CISC's combo instructions, but PA-RISC v1.1's dual pack math INT16 is useful for pixel shading like DX8 INT16 pixel shaders. 68060 lacks PA-7100LC's double SIMD32 integer pipelines.

DX8 era GPUs are streaming graphics processors. The primary use case is 3D graphics processing.

Good branch and out-of-order processing for game AI processing i.e. lessons from in-order-processing/bad branch IBM PPE vs AMD Jaguar.

Both PA-7100LC and PA-7200 have two INT units and one FP unit. PA-7100LC includes an integrated memory controller which can reduce latency e.g. K8 Athlon. 68060 doesn't include an integrated memory controller.

Classic Pentium and PA-RISC 71xx/72xx have pipelined FPU which is missing for 68060. FPU is useful for geometry e.g. Quake. DX8 era vertex shaders are already FP32.

1995 era PS1 MIPS R3000A CPU has a 33 Mhz clock speed, hence the need for Geometry Transformation Engine (GTE), but GTE has integer format, hence inferior to PC's Pentium FPU, PA-RISC FPU, and Nintendo 64's R4200 FPU. Again, the primary use case is 3D graphics processing.

1996 era Nintendo 64's MIPS R4300 CPU runs at 93.75 MHz with a theoretical 125 MIPS and 93.75 MFLOPS.

Nintendo manages to include MIPS R4200 CPU. GPU designed by the SGI team which later become ArtX which is purchased ATI. Nintendo 64's GPU is a cost-reduced OpenGL variant.
Nintendo 64 was released in 1996 in JP and 1997 in North America.

Commodore has licensed SGI's OpenGL for Amiga Hombre's GPU component.

For QuakeGL, 3DFX Voodoo supports MiniGL which is a subset of OpenGL.

NVIDIA released Riva 128 in 1997 with OpenGL support.

Quote:

PA-RISC was soon left in the dust too. Only Alpha had worse code density than PA-RISC of major RISC ISAs. At least the Alpha designers discovered quickly that the Alpha needed efficient multi-level caching while the PA-RISC designers were obsessed with minimalist cores with inadequate caching. Maybe this wouldn't have been so bad if the designs were for the embedded market but they were for workstations. Even ARM lacked enough performance without caches for most embedded use and only took off when StrongARM added more practical on chip caches. The x86 CPUs started out with inferior caching and an inferior ISA to the 68k CPUs but Intel eventually learned how to make efficient caches given many redesigns fueled by the PC clone market which propelled them past the competition.

Read http://www.cpushack.com/PA-RISC.html#2

Workstation PA-RISC CPUs have a large L2 cache.

For reference
1995 era Pentium Pro's L2 cache on the secondary die in MCM.
1997 era Pentium II's L2 cache is on the Slot 1 CPU card at half speed.
1998 era mainstream Celeron A's L2 cache is on-chip at full speed. Celeron A's lower latency has benefits for games.

1992 era PCX-L PA-7100LC has 2 MB off-die L2 cache.
1994 era PCX-T PA-7200 has 3 MB off-die L2 cache.

My classic Pentium 430VX has an on-the-motherboard 512 KB L2 cache (SRAM). 1993 era Pentium P5 has a 16 KB L1 cache.

1996 era Pentium MMX P55 has a 32 KB L1 cache.

1996 era StrongARM SA-110 is in-order processing and doesn't have branch prediction hardware.
StrongARM SA-110 has a 16 KB L1 cache.

1996 era workstation PCX-L2 PA-7300LC has 128 L1 cache and an off-die 8 MB L2 cache.

1999 era desktop mainstream AMD K7 Athlon has 128 L1 cache and L2 cache on Slot A CPU card.


Last edited by Hammer on 21-Jun-2021 at 06:20 AM.
Last edited by Hammer on 21-Jun-2021 at 06:18 AM.
Last edited by Hammer on 21-Jun-2021 at 06:15 AM.
Last edited by Hammer on 21-Jun-2021 at 06:13 AM.
Last edited by Hammer on 21-Jun-2021 at 06:10 AM.
Last edited by Hammer on 21-Jun-2021 at 06:04 AM.
Last edited by Hammer on 21-Jun-2021 at 05:43 AM.
Last edited by Hammer on 21-Jun-2021 at 05:40 AM.

_________________
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Ryzen 9 3900X, DDR4-3200 32 GB RAM, GeForce RTX 2080 Ti
Amiga 1200 (rev 1D1, KS 3.2, TF1260, 68060 @ 63 Mhz, 128 MB)
Amiga 500 (rev 6A, KS 3.2, 68K 50Mhz, 12 MB RAM)

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