Hey everyone,

I’m Leon. This September, I’m running a software development programme for a cohort of 16-18 year old T-Level students at a specialist digital engineering college in London.

They are learning modern web development (JS, DOM, CSS, JSON routing, security, design patterns), but I want to train them using the strict, resource-conscious engineering ethos of the 8 and 16-bit eras -moving away from modern framework bloat and corporate, multiple-choice certifications.

The programme is run on my platform, called THINK; I’m spending the summer setting up the tools to facilitate the programme. Instead of automated robot grading, I want the students' code to be audited by real people who actually know what optimised code looks like.

The goal is to build a network of veteran peer-reviewers. Long-term, I want to take this data to the Commodore team as a pitch for an official community-vetted Commodore Certified Developer standard - an open anti-corporate badge that carries real weight for modern tech jobs.

If you have some spare time and want to act as a code auditor when the term starts (or give feedback on the reviewer dashboard as I build it over the summer), drop a comment or DM me.

Cheers,
Leon

Last edited by 68000 on 10-Jul-2026 at 08:58 PM.

@68000

If you want to teach student something that would run on small platform, you may teach them something in on an embedded system.

Arduino comes into my mind.

@OneTimer1

Future projects will cover other languages and hardware. I'm working on a version of Blitz Basic that can be run from a web browser - with the aim being to allow students to compile this on a Amiga.

For this project, it's specifically for the web - but would be good to encourage efficient standards for the code.

68000 Quote:

Hey everyone, I’m Leon. This September, I’m running a software development programme for a cohort of 16-18 year old T-Level students at a specialist digital engineering college in London. They are learning modern web development (JS, DOM, CSS, JSON routing, security, design patterns), but I want to train them using the strict, resource-conscious engineering ethos of the 8 and 16-bit eras -moving away from modern framework bloat and corporate, multiple-choice certifications.

Interesting goal as the "8 and 16-bit eras" predate "modern web development". The "8 and 16-bit eras" were generally more resource limited than embedded hardware with networking connections today. There is a large difference between optimizing code for early 8-bit CPU memory footprints, later 8-bit CPUs using memory bank switching, a large flat address space 16-bit CPU with a 32-bit ISA as is the case for the 68000 and a mostly modern pipelined 32-bit CPU with a large flat address space as is the case for the 68020+, 80386+ and most ARM Thumb(-2) embedded CPU cores. To give an idea of early resource limitations and the problems of 16-bit pointers, I point out Steve Wozniak SWEET16 interpreted byte code instruction set.

https://en.wikipedia.org/wiki/SWEET16 Quote:

SWEET16 is an interpreted byte-code instruction set invented by Steve Wozniak and implemented as part of the Integer BASIC ROM in the Apple II computers. It was created because Wozniak needed to manipulate 16-bit pointer data, and the Apple II was an 8-bit computer. ... SWEET16 code is executed as if it were running on a 16-bit processor with sixteen internal 16-bit little-endian registers, named R0 through R15. Some registers have well-defined functions: ... According to Wozniak, the SWEET16 implementation is a model of frugal coding, taking up only about 300 bytes in memory. SWEET16 runs at about one-tenth the speed of the equivalent native 6502 code; however it shaved around 20% off the size of Integer BASIC.

The minimum memory used by modern systems for intermediate code like Android's Dalvik byte code and virtual machine, a 68k Amiga virtual machine and even an intermediate language as simple as WebAssembly is many times more memory than early 8-bit systems had. A small memory footprint starts with a good code density CPU ISA and native code. Early 8-bit accumulator architecture CPUs did not have enough of a transistor budget for many registers so generally did not have good code density and/or performance with the 6502 family being particularly poor due to minimization. As transistor budgets increased, general purpose register architectures with more and now general purpose registers became popular with CISC reg-mem architectures generally having better code density than RISC load/store architectures. Both quickly moved to 32-bit ISAs as using 32-bit pointers allowed for a much easier to use large flat address space and minimized the number of instructions executed. A further increase of transistor budgets and we had mostly modern pipelined CPUs with caches. As many embedded systems today use similar small footprint hardware, this makes the most sense to teach today unless wishing to teach CPU history through experience. Some programmers like super simplified hardware and severe resource constraints while others will feel like they are being punished. The 68k which minimizes the number of assembly instructions, minimized the amount of code and has good orthogonality is better for most programmers although popular ARM Thumb is not bad. Even if not programming in assembly, some disassembling for optimizations, debugging and low level coding is often required for small footprint systems.

68000 Quote:

The programme is run on my platform, called THINK; I’m spending the summer setting up the tools to facilitate the programme. Instead of automated robot grading, I want the students' code to be audited by real people who actually know what optimised code looks like. The goal is to build a network of veteran peer-reviewers. Long-term, I want to take this data to the Commodore team as a pitch for an official community-vetted Commodore Certified Developer standard - an open anti-corporate badge that carries real weight for modern tech jobs.

The new Commodore is stuck on Commodore 8-bit hardware for now which used mostly 6502 family CPUs. The 6502 is still alive for embedded use but using specialized MCUs for very low power applications with tiny code. It is better to choose a CPU ISA with better code density if using more than a few kiB of memory. Non 8-bit neo Commodore hardware seems to be moving to bloated systems. It is difficult to encourage a code optimization standard with poor code density 6502 family CPUs and when the business does not practice it themselves. Making tiny memory footprint hardware may be enough to encourage tight code in the case of retro 8-bit hardware. The problem is that even a 16-bit or 32-bit 6502 family CPU will never be as modern as even a 68000 CPU. The 68060 is practically modern except for the old silicon with code density competitive with Thumb-2 and encoding space for improvements. I believe performance could be competitive if not better than other in-order cores with new silicon and basic enhancements. The 32-bit 68k AmigaOS provides synergies for a small memory footprint which standard Linux can not come close to. There was an Amiga Certified Software Engineer (ACSE) certification, which was done in cooperation with the Amiga Qualifications Working Group (AQWG).

Proposal: How about a professional Amiga certification?
https://eab.abime.net/showpost.php?p=925221&postcount=32

I passed the ACSE test and received a virtual certificate by e-mail many years ago. I do not know if it is available anymore although Minuous, his website and his software are still around. It was possible to register Amiga AutoConfig hardware expansion IDs through Minuous's software which went to AmigaOS developers too. He more recently became part of the 68k AmigaOS dev team before leaving the team. These are the kinds of support that die without competitive hardware and it is very difficult to develop something that is dying. RPI has educational support but they have solidified themselves as a major hardware producer with a market cap of £1.62 billion (~$2.17 billion USD). RPI is more like the old Commodore than the new Commodore.

68000 Quote:

Future projects will cover other languages and hardware. I'm working on a version of Blitz Basic that can be run from a web browser - with the aim being to allow students to compile this on a Amiga. For this project, it's specifically for the web - but would be good to encourage efficient standards for the code.

Compiling is a challenge on even the last Amiga hardware standard of a 68EC020 and 2 MiB of memory but is no problem on even the original 512 MiB $35 USD RPi. The original Amiga with 256 kiB is closer in spec to the 520 kiB SRAM RP2350 MCU that sells for ~$1 USD in the Raspberry Pi Pico 2 SBC that sells for ~$5 USD (Pico 2 W with Wi-Fi and Bluetooth is $7 USD).

https://en.wikipedia.org/wiki/RP2350

There is no standard OS like the 68k AmigaOS for the small footprint RPi MCUs while the 68k AmigaOS even comes with a GUI. The RP2350/Pico is a nice, cheap and available small footprint MCU for learning though. It includes ARM Thumb-2 and RISC-V (RVC) cores which is good for education purposes. The non-MCU RPis offer better value in many cases but a small footprint MCU can offer reduced latency if willing to hit the hardware.

GigaNES
https://projecthub.arduino.cc/kaled4809/giganes-cdcb87 Quote:

In the field of emulation, the $ STM32H747XI $ delivers disruptive performance. Although it is a dual-core SoC, its 480 MHz Cortex-M7 core is the true standout: thanks to its superscalar architecture and zero-latency Tightly Coupled Memory (TCM) , it processes video layers and transparencies with a fluidity that popular alternatives simply cannot match. While the ESP32 (Xtensa at 240 MHz) or the RP2040/RP2350 (Cortex-M0+/M33 at 150 MHz) often encounter data access bottlenecks, this chip ensures consistent 60Hz (NTSC) emulation, high-fidelity audio via its 12-bit DAC , and imperceptible input lag. This undoubtedly positions this project as the most advanced and powerful NES emulator ever developed for the Arduino ecosystem. Unlike typical portable emulation projects based on Single-Board Computers (SBCs) like the Raspberry Pi 5 or Orange Pi, $ GigaNES $ operates entirely on bare-metal hardware . While high-performance MPUs rely on a complex Linux operating system layer—which introduces multi-threaded scheduling overhead, driver abstraction, and unpredictable input lag (ranging from 15 to 50 ms)—this project achieves a near-zero latency (< 1 ms) gaming experience. By avoiding the heavy overhead of an OS kernel, the Cortex-M7 core samples controller inputs through direct low-level register access in a deterministic manner. Furthermore, this MCU-centric design eliminates data corruption risks during sudden power-offs, boots instantly in under a second, and operates with extreme thermal efficiency, delivering a silent, fanless, and robust console experience that modern MPU-based alternatives cannot replicate.

The Arduino MCU mentioned has 1MiB of memory (864 KiB of user SRAM) but the SBC is $69.60 USD, expensive compared to RPi SBCs.

https://store.arduino.cc/collections/giga/products/giga-r1-wifi

No standard OS but low latency emulation gaming for a price. A 68k Amiga with a similar memory footprint could have a standard AmigaOS with a large library of software that could be downloaded but no 68k Amiga hardware showed up to compete in Amiga Neverland.

@68000

Quote:

68000 wrote: I want the students' code to be audited by real people who actually know what optimised code looks like.

What a horrible job.

I have a better idea - get your students to write a program that knows what optimized code looks like and use that. Of course its first job would be to audit itself. :)

@bhabbott

Ha, the recursive self-auditing compiler - the ultimate developer dream!

You're not wrong, reading messy junior code is brutal. To prevent it from being a horrible job, I already have an LLM integration on the backend to use as a "first pass". This was created for giving students the ability to get feedback on their homework code - so it 's a good fit for this project.

The AI automatically flags the obvious stuff (like redundant loops or giant functions) and pre-selects the rubric tags. The human reviewer's job is just to look at the 10-line snippet, verify if the AI is right, tweak it if needed, and hit submit. Turns a tedious audit into a 60-second sanity check over a coffee break!

@matthey

You are speaking my language here. The maths on instruction multi-issue rates and code density for the 68060 is exactly the type of engineering elegance that has been completely lost in modern enterprise software.

To clarify the context: the college course piloting the THINK platform is a broader software development T-Level programme. We are using web architecture as our initial thematic framework because it's highly accessible, but the ultimate goal is true computational literacy.

However, THINK itself isn't a web-only platform. Behind the scenes, I've developed modules for everything from Little Man Computer (LMC) assembly to complex data structures like linked lists and Dijkstra's algorithm. I want to break these students out of the habit of treating modern computers like infinite resource machines. If they learn to respect loops, pointers, and memory constraints now, they will be infinitely better prepared if they progress into the low-level, deterministic embedded worlds you are talking about.

The other part of the project and THINK as a whole, is about helping people to recognise how to learn and work online.

I firmly believe that the future of engineering work is asynchronous and distributed. By keeping the code, the micro-review queues, and the dashboard entirely in the browser, it teaches the students how real-world distributed teams collaborate across borders. They learn to push code, receive asynchronous feedback from an industry professional, and iterate without needing to sit in a physical room together.

Because you understand low-level structural optimisation so intimately, I’d value your perspective on the concept.

It would be good have your opinion on how it works and how it could allow reviewers to give useful input without just a few minutes of their time. Would you be open to trying the dashboard when I have it online?

Cheers,
Leon

68000 Quote:

You are speaking my language here. The maths on instruction multi-issue rates and code density for the 68060 is exactly the type of engineering elegance that has been completely lost in modern enterprise software.

Maybe you have been lurking without posting hear for awhile? It sounds like maybe you have been reading some of the threads here like cdimauro's code density thread?

The (Microprocessors) Code Density Hangout
https://amigaworld.net/modules/newbb/viewtopic.php?topic_id=44169&forum=17

"Elegance" is a word I have used to describe the 68k too. The 1979 68000 had the elegant 32-bit ISA that created the 32-bit embedded market which the 68k led through at least 1997, created the MPU workstation market, gained roughly 35%-45% of the desktop and workstation market according to AI and gained roughly 43%-45% of the console market according to AI. The orthogonality and code density of the 68000 allowed the 68000 to outperform the 8086, 80186 and 80286 up through 1985. The 68020 ISA enhancements were hit and miss but the 68020/68030 outperformed the 80386, the 68040 had better integer performance/MHz than the 80486 and the 68060 had better integer performance/MHz than the Pentium, by ~40% according to the ByteMark benchmark. With the 1994 68060, the 68k finally had the elegant CPU design to match the elegant ISA. The 8-stage instruction pipeline, decoupled instruction fetch pipeline (IFP) with instruction buffer, dual integer execution pipelines that can perform a data access each (AGU+ALU in each OEP), decoupled store buffer, dynamic branch prediction, predicted branch folding eliminating even the branch overhead, etc. more resembles modern in-order designs than competitor designs at the time. Many in-order CPU core designs today are generic with the exception of the RISC-V SiFive series 7 design which resembles the 68060 design but the RISC-V ISA is weaker than the 68k ISA. The design was still worth it with a RISC load/store ISA because of the minimization of stalls. Difficult instruction scheduling of code to avoid stalls results in larger code, for example with more loop unrolling and inlined functions. The bonus of a CPU design like the 68060 which minimizes stalls and has a clean ISA is that preexisting code can have good performance as the 45%-55% of instructions multi-issued for preexisting code on the 68060 demonstrates. The 68060 started with a low power superscalar design for embedded use even though a 68060+ with 20%-30% performance increase at the same clock speed was planned for the modular design along with a scalar 68060Lite version. Moto joined the AIM alliance with most development efforts directed toward politically chosen fat PPC and the 68EC060 and 68LCO60 feature downgrades were all that the elegant 68060 ever received although the design was reused for the simplified ColdFire V4 (like simplified 68060Lite) and ColdFire V5 (like simplified 68060). Chief architect of the 68060 Joe Circello has Amiga connections and recently did an interview in an Amiga Bill video if you missed that.

Inside the Motorola 68060 & Chip Design: Interview with Lead Designer Joe Circello!
https://www.youtube.com/watch?v=1takr2k7Yfo

The video only has 17k views and 234 comments in a month as it is likely too technical and detached from 68k gaming for most retro fans I guess. The 68k is popular when connected with gaming though as the following Modern Vintage Gamer video demonstrates with 598k views and 1,813 comments in 1 year.

68000 - The CPU ahead of its time
https://www.youtube.com/watch?v=njGWWg69B4A

Teaching kids a little history before having them use the 68k would likely increase interest for what some students may think is an outdated architecture and teacher that uses it. In some ways this is still true with no affordable hardware and outdated silicon even though the tech could be brought forward and would be one of the easiest to program architectures and one of the best architectures for small memory footprint systems, at least on par and perhaps even smaller footprint than Thumb-2. I learned 68k assembly programming in college on 68000 Atari STs at around the time they were discontinued. I expect it would be difficult to buy any small memory footprint systems for a classroom but RPi hardware considering the price. I have suggested developing a 68k SoC ASIC for small memory footprint 68k hardware to compete with RPI but Trevor loves his PPC and milking customers of extremely low production hardware for the classes and not the school classes. Mike and maybe Christian may have other plans for the masses though.

68000 Quote:

To clarify the context: the college course piloting the THINK platform is a broader software development T-Level programme. We are using web architecture as our initial thematic framework because it's highly accessible, but the ultimate goal is true computational literacy. However, THINK itself isn't a web-only platform. Behind the scenes, I've developed modules for everything from Little Man Computer (LMC) assembly to complex data structures like linked lists and Dijkstra's algorithm. I want to break these students out of the habit of treating modern computers like infinite resource machines. If they learn to respect loops, pointers, and memory constraints now, they will be infinitely better prepared if they progress into the low-level, deterministic embedded worlds you are talking about.

Modern x86-64 desktop programmers are the worst. Many early x86 programmers learned assembly and optimization which gave an advantage over RISC competitors. Now it is bloated compilers doing most of the optimization with job security due to the compilers not working well on lesser hardware. Eben Upton understood the problem in developing the small memory footprint RPi for education. Did he have more influence from his smaller memory footprint Amiga 600 or the RPi spiritual predecessor the Acorn Archimedes though?

Your "programme" sounds like fun. I had a few computer related courses including data structures but I expect I could learn a few things from your programme too. There is much to know about computers.

68000 Quote:

The other part of the project and THINK as a whole, is about helping people to recognise how to learn and work online. I firmly believe that the future of engineering work is asynchronous and distributed. By keeping the code, the micro-review queues, and the dashboard entirely in the browser, it teaches the students how real-world distributed teams collaborate across borders. They learn to push code, receive asynchronous feedback from an industry professional, and iterate without needing to sit in a physical room together.

Right. The most important thing to learn in school is how to learn. Everything in a web browser is the direction we seem to be headed even as browser requirements climb. Much of it is due to browser related bloat but higher level languages and more abstraction make optimization more difficult.

68000 Quote:

Because you understand low-level structural optimisation so intimately, I’d value your perspective on the concept. It would be good have your opinion on how it works and how it could allow reviewers to give useful input without just a few minutes of their time. Would you be open to trying the dashboard when I have it online?

Most of my programming experience is with the 68k Amiga. I can look at disassembled 68k programs, see how optimized the code is and even start optimizing it but the 68k is easy. The hard part is getting compilers and compiler developers to improve their optimizations. I was on the VBCC team, helped develop 68k and ColdFire optimizations, improved the 68k FPU support and improved C99 support. I was on the Apollo team helping with ISA development and optimizations of benchmarks for the Apollo 68k FPGA CPU core. I further developed an existing 68k disassembler called ADIS which is the largest C program I have worked on.

ADis disassembler
https://eab.abime.net/showthread.php?t=82709

I have a few smaller projects on EAB and Aminet as well. I was pretty good with BDebug from the Barfly package on Aminet. I have helped various developers with optimizations including 68k Amiga FFMPEG, the official 68k Amiga NetSurf, multiple versions of Quake, etc. I helped Dr. Vince Weaver with his code density contest.

http://deater.net/weave/vmwprod/asm/ll/ll.html

That code density contest is more interesting because it includes many retro and some embedded architectures. Unfortunately, it does not seem to be updated anymore as the last submitted 68k improvements were not updated. I have lost motivation in programming too as my 68k Amiga hardware dies, the 68k and Amiga platform dies and is replaced by EOL emulation and due to being attacked on Amiga forums. Everything I have done for the 68k and Amiga I did for free but no good deed goes unpunished and 68k Amiga NeverLand seems to be never ending. My computer related education is limited and my computer experience is unique but maybe it would be useful to test your project?

Last edited by matthey on 13-Jul-2026 at 01:08 PM.

@matthey

I've been watching the forums for years but never posted.

You're right about teaching the history behind what people learning. This makes the concepts more relatable and gives more indepth understand on why things are done the way they are.

Data structures are pretty useful for keeping code maintainable. The right data structures allow complicated solutions without complicated code.

Seeing your involvement with VBCC, the Apollo core, and your work on code density contests -is the the type of expert calibration that would be great to have in the project. Students would benefit from insights to instruction scheduling and resource management for their courses and also in application.

The 68k Amiga has missed opportunities - but things might be looking up if the new Commodore can get the different parties working together.

Hey everyone,

As promised, I've put together the central concept page outlining the modular validation framework we’ve been discussing:

👉 https://openverified.org/concept.html

The first functional utility is now live. I’ve built a decentralised certificate tool that allows developers to generate cryptographic proof of their validated work fragments detailing who verified it and what the work was about. All details are stored in the links - so these digital certificates can be embedded into CVs and social platforms like Linkedin and GitHub.

It would be great to hear your thoughts - including on how it could be used to encourage people to develop Amiga projects.

Cheers,
Leon

Oh my....
The infection is growing.
It has nigh on cloned itself at this point.

@fishy_fis

No "Web3" or crypto-currency nonsense here, just traditional boring web engineering - not a blockchain scheme.

To clarify what "decentralised" and "cryptographic" actually mean in this context:

* Decentralised: It just means there is no OpenVerified database storing the candidates' personal details or portfolios. The candidate hosts their own files (on GitHub, their own server, etc.).

* Cryptographic: We are using basic public-key cryptography (like SSH keys or PGP signatures, which have been around since the 90s) to sign a hash of the work fragment.

It’s just standard security signatures to prove a file hasn't been tampered with since the assessor reviewed it. No tokens, no mining, no ledger, and zero hype. Just standard, lightweight code.

Cheers,
Leon

@68000

Quote:

👉 https://openverified.org/concept.html

As for me, I found this concept to be very compelling, with potential for a broader industry appeal via your linkedin/github exposure. However, I can't claim to have recent knowledge of any alternatives or competitors to know how unique your concept is.

Of course, the THINK programme that underpins these certifications will be where those certifications earn their weight and credibility. A related challenge I think your platform and assessor network could help to address is to identify those students who are using AI too heavily, thereby impairing their independent understanding and problem solving skills.

Quote:

I want to take this data to the Commodore team as a pitch for an official community-vetted Commodore Certified Developer standard

Commodore has expressed some interest in this. I think Perry called it the "Commodore Kids" program, but it might be aimed a bit younger than the 16-18 range you mentioned. And if these certifications become relevant on linkedin/github, then Commodore could (in theory) see some benefits from that - of course, that's a super optimistic hope. But Perry seems open to optimism.

However, I suspect for Commodore to be motivated by your pitch, your THINK platform might have to take a page from approaches like these videos demonstrate for combining new tech with retro tech:

https://www.youtube.com/watch?v=7sLTaVWV0c8
https://www.youtube.com/watch?v=gNC_A03zRbg


Personally, I think a very interesting retro-inspired learning environment could be built on these ideas. For example, build some foundational code that students can leverage to more quickly build a game, that can then be deployed to a C64U, and eventually a Commodore Callback. Maybe something like like this but maybe with more full-code capabilities:

https://www.youtube.com/watch?v=P6JQYxixYbo (new, looks very interesting)

Why would this be motivating to a young mind? Well, this is my own soap box, but IMO, it is partly because kids today miss something basic that we all had - an open console they can program and learn on. In that respect PS5 is half the console we had in 1983 via the C64. And I think kids never lost their interest in learning and programming an open console -- we adults just took that capability away from them.

Last edited by jingof on 16-Jul-2026 at 08:18 PM.
Last edited by jingof on 16-Jul-2026 at 07:45 PM.
Last edited by jingof on 16-Jul-2026 at 05:06 PM.

_________________
Vic-20, C-64, C-128
Amiga 1000, 3000
AmigaOne X1000

@jingof

Positioning verification as the defence against AI cheating is a good angle I didn't think about. Part of the way it solves this is by reviewing how candidates are able to justify their decisions. It would be great to hear of any other ideas to detect AI cheating.

Your mention of Peri's "Commodore Kids" program is interesting, as the main THINK product is designed for this age range. Here's the details of the games development curriculum:

https://thinkskills.net/make

They learn to build these projects using Blitz Basic, which we use for the rocket simulator on that page.

To bridge the modern and retro worlds, I’ve set up a working prototype inside THINK that runs a fully functional Amiga emulator directly in the browser;. It can take the Blitz Basic code that students write in the web interface and passes it to the browser-based Amiga emulator, allowing student creations to be compiled as a real Amiga app.

Blitz Basic is a useful gateway to modern software development, with high level programming, while 6502/C64 assembly seems a good fit for introducing people to low-level programming and understanding hardware constraints.

The video tutorials you linked to look good - I will have to check them out properly when I have the time. I have some tutorial videos created for tuition lessons I deliver - you're right about it being handy to package video with interactive learning resources to make it easier for people to understand the concepts.

@68000

Quote:

To bridge the modern and retro worlds, I’ve set up a working prototype inside THINK that runs a fully functional Amiga emulator directly in the browser;. It can take the Blitz Basic code that students write in the web interface and passes it to the browser-based Amiga emulator, allowing student creations to be compiled as a real Amiga app.

I really like your approach here. But you also mentioned pitching to Commodore in your OP. My only point is that Commodore probably won't be motivated by that if you are pitching to them. They don't own anything in Amiga land, and probably never will IMO. I'd love to be wrong on that point.

Quote:

while 6502/C64 assembly seems a good fit for introducing people to low-level programming and understanding hardware constraints

Agreed. Potentially, a course on assembly language with a C64U deployment target would be motivating to Commodore. But I understand that is a lot of work for "potentially".

Quote:

It would be great to hear of any other ideas to detect AI cheating.

This is a hard problem. And I don't think AI should be eliminated, just brought in at the right point in their understanding. In fact, a course on AI and vibe coding should probably be part of your curriculum. However, that should only come after students have proven that they are not using AI as too much of a crutch. The course itself would probably be so sought after, that students would seek to prove their independence from AI so that they can qualify to take the vibe coding class. And the gate that opens the vibe coding opportunity to them is an interactive interview and/or proctored test that ensures they can do the work without AI in their pocket.

_________________
Vic-20, C-64, C-128
Amiga 1000, 3000
AmigaOne X1000

@68000

Quote:

68000 wrote: @bhabbott The AI automatically flags the obvious stuff (like redundant loops or giant functions) and pre-selects the rubric tags. The human reviewer's job is just to look at the 10-line snippet, verify if the AI is right, tweak it if needed, and hit submit. Turns a tedious audit into a 60-second sanity check over a coffee break!

This is the world we live in now, humans are just curators of AI.

Back in the 1960's my father (a simple farmer) told me what life would be like in the 21st century. He said humans would develop bigger thumbs because all they would be doing is pressing buttons. He wasn't far off!

Last edited by bhabbott on 17-Jul-2026 at 05:27 PM.

Quote:

matthey wrote: 68000 Quote: Hey everyone, I’m Leon. This September, I’m running a software development programme for a cohort of 16-18 year old T-Level students at a specialist digital engineering college in London. They are learning modern web development (JS, DOM, CSS, JSON routing, security, design patterns), but I want to train them using the strict, resource-conscious engineering ethos of the 8 and 16-bit eras -moving away from modern framework bloat and corporate, multiple-choice certifications. Interesting goal as the "8 and 16-bit eras" predate "modern web development". The "8 and 16-bit eras" were generally more resource limited than embedded hardware with networking connections today. There is a large difference between optimizing code for early 8-bit CPU memory footprints, later 8-bit CPUs using memory bank switching, a large flat address space 16-bit CPU with a 32-bit ISA as is the case for the 68000 and a mostly modern pipelined 32-bit CPU with a large flat address space as is the case for the 68020+, 80386+ and most ARM Thumb(-2) embedded CPU cores. To give an idea of early resource limitations and the problems of 16-bit pointers, I point out Steve Wozniak SWEET16 interpreted byte code instruction set. https://en.wikipedia.org/wiki/SWEET16 Quote: SWEET16 is an interpreted byte-code instruction set invented by Steve Wozniak and implemented as part of the Integer BASIC ROM in the Apple II computers. It was created because Wozniak needed to manipulate 16-bit pointer data, and the Apple II was an 8-bit computer. ... SWEET16 code is executed as if it were running on a 16-bit processor with sixteen internal 16-bit little-endian registers, named R0 through R15. Some registers have well-defined functions: ... According to Wozniak, the SWEET16 implementation is a model of frugal coding, taking up only about 300 bytes in memory. SWEET16 runs at about one-tenth the speed of the equivalent native 6502 code; however it shaved around 20% off the size of Integer BASIC. The minimum memory used by modern systems for intermediate code like Android's Dalvik byte code and virtual machine, a 68k Amiga virtual machine and even an intermediate language as simple as WebAssembly is many times more memory than early 8-bit systems had. A small memory footprint starts with a good code density CPU ISA and native code. Early 8-bit accumulator architecture CPUs did not have enough of a transistor budget for many registers so generally did not have good code density and/or performance with the 6502 family being particularly poor due to minimization. As transistor budgets increased, general purpose register architectures with more and now general purpose registers became popular with CISC reg-mem architectures generally having better code density than RISC load/store architectures. Both quickly moved to 32-bit ISAs as using 32-bit pointers allowed for a much easier to use large flat address space and minimized the number of instructions executed. A further increase of transistor budgets and we had mostly modern pipelined CPUs with caches. As many embedded systems today use similar small footprint hardware, this makes the most sense to teach today unless wishing to teach CPU history through experience. Some programmers like super simplified hardware and severe resource constraints while others will feel like they are being punished. The 68k which minimizes the number of assembly instructions, minimized the amount of code and has good orthogonality is better for most programmers although popular ARM Thumb is not bad. Even if not programming in assembly, some disassembling for optimizations, debugging and low level coding is often required for small footprint systems. 68000 Quote: The programme is run on my platform, called THINK; I’m spending the summer setting up the tools to facilitate the programme. Instead of automated robot grading, I want the students' code to be audited by real people who actually know what optimised code looks like. The goal is to build a network of veteran peer-reviewers. Long-term, I want to take this data to the Commodore team as a pitch for an official community-vetted Commodore Certified Developer standard - an open anti-corporate badge that carries real weight for modern tech jobs. The new Commodore is stuck on Commodore 8-bit hardware for now which used mostly 6502 family CPUs. The 6502 is still alive for embedded use but using specialized MCUs for very low power applications with tiny code. It is better to choose a CPU ISA with better code density if using more than a few kiB of memory. Non 8-bit neo Commodore hardware seems to be moving to bloated systems. It is difficult to encourage a code optimization standard with poor code density 6502 family CPUs and when the business does not practice it themselves. Making tiny memory footprint hardware may be enough to encourage tight code in the case of retro 8-bit hardware. The problem is that even a 16-bit or 32-bit 6502 family CPU will never be as modern as even a 68000 CPU. The 68060 is practically modern except for the old silicon with code density competitive with Thumb-2 and encoding space for improvements. I believe performance could be competitive if not better than other in-order cores with new silicon and basic enhancements. The 32-bit 68k AmigaOS provides synergies for a small memory footprint which standard Linux can not come close to. There was an Amiga Certified Software Engineer (ACSE) certification, which was done in cooperation with the Amiga Qualifications Working Group (AQWG). Proposal: How about a professional Amiga certification? https://eab.abime.net/showpost.php?p=925221&postcount=32 I passed the ACSE test and received a virtual certificate by e-mail many years ago. I do not know if it is available anymore although Minuous, his website and his software are still around. It was possible to register Amiga AutoConfig hardware expansion IDs through Minuous's software which went to AmigaOS developers too. He more recently became part of the 68k AmigaOS dev team before leaving the team. These are the kinds of support that die without competitive hardware and it is very difficult to develop something that is dying. RPI has educational support but they have solidified themselves as a major hardware producer with a market cap of £1.62 billion (~$2.17 billion USD). RPI is more like the old Commodore than the new Commodore. 68000 Quote: Future projects will cover other languages and hardware. I'm working on a version of Blitz Basic that can be run from a web browser - with the aim being to allow students to compile this on a Amiga. For this project, it's specifically for the web - but would be good to encourage efficient standards for the code. Compiling is a challenge on even the last Amiga hardware standard of a 68EC020 and 2 MiB of memory but is no problem on even the original 512 MiB $35 USD RPi. The original Amiga with 256 kiB is closer in spec to the 520 kiB SRAM RP2350 MCU that sells for ~$1 USD in the Raspberry Pi Pico 2 SBC that sells for ~$5 USD (Pico 2 W with Wi-Fi and Bluetooth is $7 USD). https://en.wikipedia.org/wiki/RP2350 There is no standard OS like the 68k AmigaOS for the small footprint RPi MCUs while the 68k AmigaOS even comes with a GUI. The RP2350/Pico is a nice, cheap and available small footprint MCU for learning though. It includes ARM Thumb-2 and RISC-V (RVC) cores which is good for education purposes. The non-MCU RPis offer better value in many cases but a small footprint MCU can offer reduced latency if willing to hit the hardware. GigaNES https://projecthub.arduino.cc/kaled4809/giganes-cdcb87 Quote: In the field of emulation, the $ STM32H747XI $ delivers disruptive performance. Although it is a dual-core SoC, its 480 MHz Cortex-M7 core is the true standout: thanks to its superscalar architecture and zero-latency Tightly Coupled Memory (TCM) , it processes video layers and transparencies with a fluidity that popular alternatives simply cannot match. While the ESP32 (Xtensa at 240 MHz) or the RP2040/RP2350 (Cortex-M0+/M33 at 150 MHz) often encounter data access bottlenecks, this chip ensures consistent 60Hz (NTSC) emulation, high-fidelity audio via its 12-bit DAC , and imperceptible input lag. This undoubtedly positions this project as the most advanced and powerful NES emulator ever developed for the Arduino ecosystem. Unlike typical portable emulation projects based on Single-Board Computers (SBCs) like the Raspberry Pi 5 or Orange Pi, $ GigaNES $ operates entirely on bare-metal hardware . While high-performance MPUs rely on a complex Linux operating system layer—which introduces multi-threaded scheduling overhead, driver abstraction, and unpredictable input lag (ranging from 15 to 50 ms)—this project achieves a near-zero latency (< 1 ms) gaming experience. By avoiding the heavy overhead of an OS kernel, the Cortex-M7 core samples controller inputs through direct low-level register access in a deterministic manner. Furthermore, this MCU-centric design eliminates data corruption risks during sudden power-offs, boots instantly in under a second, and operates with extreme thermal efficiency, delivering a silent, fanless, and robust console experience that modern MPU-based alternatives cannot replicate. The Arduino MCU mentioned has 1MiB of memory (864 KiB of user SRAM) but the SBC is $69.60 USD, expensive compared to RPi SBCs. https://store.arduino.cc/collections/giga/products/giga-r1-wifi No standard OS but low latency emulation gaming for a price. A 68k Amiga with a similar memory footprint could have a standard AmigaOS with a large library of software that could be downloaded but no 68k Amiga hardware showed up to compete in Amiga Neverland.

lol

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I HAVE ABS OF STEEL
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CAN YOU SEE ME? CAN YOU HEAR ME? OK FOR WORK

@68000

Now, quess which one gets employed...

Guy with experience with JS, DOM, CSS, JSON routing, security, design patterns or one with 6502 assembler and blitz basic.

You really got to hate the kids....

@jingof

Thanks for the feedback.

To clarify the IP side, the browser feature is a purely technical prototype to prove the execution model. The Blitz Basic implementation is entirely my own open-source engine, so there are no licensing blockers there - it simply compiles and runs the language syntax. If the project shifts focus toward the 8-bit ecosystem to align with Commodore’s actual assets, the compiler pipeline can be adapted to target the C64/6502 architecture.

On the AI curriculum point, your perspective on the psychology is spot on. Using the advanced toolset as an incentive that must be earned changes the dynamic completely. It turns the anti-cheat defence into a milestone rather than a restriction.

There is a massive spectrum to how AI is deployed. Pure "vibe coding" - where someone drops in a vague specification and blindly trusts the output—is highly problematic for engineering discipline. However, using AI as a junior developer to fetch snippets, automate boilerplate, or iteratively refine an algorithm under close human supervision is a major productivity driver.

In fact, responsible use of AI actually increases the premium on code-reading literacy and pattern recognition. Historically, amateur developers frequently abandoned legacy code on small business projects because reading and reverse-engineering another human's logic is exceptionally difficult. AI compounds this problem: it can generate hundreds of lines of complex structure in seconds.

If a developer lacks the baseline literacy to scan code, recognise common patterns, and audit AI output for subtle logical hallucinations, they will end up buried under unmaintainable architecture. Structuring the curriculum so students first master the bare metal ensures they have the deep reading comprehension required to manage these AI agents effectively. The vocal defence remains the gatekeeper to ensure they actually understand the logic being deployed.

@Rose

You are misunderstanding the structure of the program. The certification is completely focused on modern industry skills - such as JavaScript, JSON, PHP, security, and web design patterns.

To clarify the exact relationship between the components:

The Certification Stack: The college program explicitly evaluates candidates on their mastery of the modern web stack (JS, PHP, DOM, JSON routing). The example certificate on the OpenVerified page shows this exact industry focus.

The Project Focus (THINK): Students are certified based on their work following and developing the THINK product framework itself—which is built on the modern web technologies listed above.

The Retro Principles: While THINK incorporates Blitz Basic as part of its internal product content, the students are not being certified in writing Blitz Basic. Similarly, the reference to 6502 is not about writing machine code; it is a conceptual study used to teach structural code efficiency, algorithmic optimisation, and working under strict hardware constraints.

The goal is to certify developers who can build modern enterprise applications, but who also possess the deep, algorithmic discipline that comes from understanding how software interacts with hardware constraints.