Mai to make northbridge that can handle the IBM 970?
Date 20-Jun-2003 9:36:26
Topic: Hardware News
| This is a summary from Ars Technica's forums.
Report from the 2003 IBM Technology Group
New England Design Forum
June 18, 2003
There were interesting introductory, and business-wide talks, including an extended talk by Dr. Robert Guernsey, Director of Silicon Technology Strategy for IBM. I may report some of those later. Here I will cover only the 970, and at the end a few tidbits gained from talking to exhibitors.
The 970 presentation was given by J. Rogers, PowerPC Product line manager. He gave an overview of the 970 which I will not summarize, because it was substantially similar to the IBM presentation at the micro-F.
New attributable points/facts (at least to me) include:
* about the "elastic bus:" it is a direct p2p bus, it is NOT a ring topology, and memory controllers for MP systems will require 1 E-bus per processor.
* E-bus supports 21 outstanding transactions (i.e. out of order)
* all control, address, and data travel on the E-bus. {I have a query to verify/elaborate some issues of this, compared to the figure from the micro-F, particularly about snoop/snarf MP transactions}
* "all memory fetches {on the E-bus} are 32 bytes" -- this is literally what was said, I have a query in on this to elaborate.
Note that this says MEMORY fetches; there are some interesting issues with respect to volatile hardware registers if this block size were universal... also this doesn't say anything about write transactions... which would be problematic too for volatile writes unless there was a finer-grained write mechanism. This 32-byte block corresponds to a "4 beat access" on 603/MPXbus. I presume there are smaller-grained accesses for hardware transactions that need them.
* IBM is developing a memory controller (specifically described as "Northbridge" which will be for general sale, and IBM will sell development/prototyping systems using it.
* IBM is actively talking "to memory controller vendors with representatives in this room (Mai Logic and Marvell were exhibiting) and others, who will vend controllers supporting at least dual CPUs."
* In response to a question by me, Jim stated Xilinx FPGAs can be used to synthesize Elastic-Bus interfaces "but not very fast." He also volunteered that IBM did so for very early prototype work, only. I noted the connection between IBM and Xilinx, and urged that the Xilinx capability be improved if possible, because it would permit embedded-systems designers much more flexibility for low-volume products (and rapid prototyping).
* In response to a question from the floor, Jim Rogers stated that current 970s consume 20W at 1 GHz, and 50W at 1.8 GHz. These numbers drew gasps from some of the embedded-oriented PPC engineers in the audience (who are accustomed to simple integer cores like the 40x and 44x series... and expect single-digit watts... and not too many of them). These are creditable power levels for this performance and 0.13 micron.
* limited sampling is proceeding now
* Jim also emphasized that 970 will be optimized to have a wide voltage/Hz operability band; the customer can select the operating point. He showed examples of 405 "speed-stepping" with transition times as fast as 100 microseconds... and strongly hinted this capability would come to the 970 family
* XLC was directly compared to Intel's proprietary "performance compiler." In response to a question by me Jim stated that XLC will be augmented to take advantage of Altivec instructions, including specifically autovectorization. He also noted that IBM is working to ensure that gcc will generate code optimized for 970, the latter effort of course building on the extensive Power4 heritage.
* In response to my question Jim stated that the 970 can sustain a VPERM, a VALU, and TWO vector load/store instructions per cycle (This is a very substantial improvement compared to Moto's with respect to spill-code. It also makes many issues of auto-vectorization much easier.)
* There was a very general (but extended) exposition about the advantages of multi-threading, and the clear "roadmapish" statement that the 970 family will provide that in the future. The ability to allocate one hardware thread to interrupts was specifically mentioned. No specific time was given.
* Similarly there was a general exposition of memory latency issues (which are of course directly related to SMT issues), and in response to a question from the floor the advantages of integrated memory controllers were warmly compared to Opteron, and again the "roadmapish" statement made that IBM will provide such, but no time given.
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