P.A. Semi Unveils New PPC Multicore Processor Family
Date 24-Oct-2005 12:30:36
Topic: Hardware News
| Official press release [Thanks to Fisk for the link].
A The Inquirer article on said chip [Thanks to DrBombcrater for the link].
Today P.A. Semi announced the PA6T-1682M. A new multicore, low power PPC chip that is stated to dissapate between 5-13 watts running at 2Ghz, with a high level of integration (memory controller PCI-E, Ethernet, etc).
Read on for select bits of the official press release:
THE PWRficient PROCESSOR ROLLOUT
The first PWRficient chip, the PA6T-1682M, which dissipates between just 5-13 watts, depending upon the application, is a dual-core implementation running at 2GHz with two DDR2 memory controllers, 2MB of L2 cache, and a flexible I/O subsystem that supports eight PCI Express controllers, two 10 Gigabit Ethernet XAUI controllers, and four Gigabit Ethernet SGMII controllers sharing 24 serdes lanes. It will sample in the third calendar quarter of 2006, with single-core and quad-core versions due in early and late 2007, respectively, and an eight-core version planned for 2008.
PWRficient ARCHITECTURAL ELEMENTS
The PWRficient family of platform processors is derived from a common set of fundamental architectural elements. A coherent, ordered crossbar called CONEXIUMTM interconnects multiple Power cores, L2 caches, memory controllers, and the ENVOITM I/O subsystem. ENVOI combines a set of configurable serdes lanes with a set of protocol controllers for such I/O standards as PCI Express, Gigabit Ethernet, and 10 Gigabit Ethernet.
These controllers share a bridge to CONEXIUM, as well as a set of centralized DMA channels, offload engines, and a coherent I/O cache. The architecture supports a variety of offload engines, including support for TCP/IP, iSCSI, cryptography (IPSec and SSL), and RAID. This layered, scalable architecture results in versatile single-chip solutions that can be quickly developed by combining the appropriate number of Power cores, memory controllers, and L2 caches with a suitable number of serdes lanes and protocol controllers.
P.A. Semi also employs a unique scalable-socket plan, which provides several options for performance upgrades or cost reductions with little or no design effort. P. A. Semi defines a "socket" (package, pinout, and power envelope) by the number of memory controllers (up to four), the number of serdes I/O lanes (up to 32), and the supported system peripherals. Each socket supports several performance levels by varying the number of cores (up to eight on a chip) and the size of the L2 cache (up to 8MB). Within a socket definition, processors are tailored to different applications by adjusting the number and type of the high-speed I/O protocols (for example PCI Express, 10 Gigabit Ethernet, 1 Gigabit Ethernet, SATA/SAS, RapidIO, and Fibre Channel). Initial socket definitions include the "E" socket (entry), "M" socket (midrange), and "P" socket (performance). Customers can design to a specific socket, instead of a specific processor, to enable easy migration to compatible processors.
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