@WolfToTheMoon

True. However it is one of the most active areas in a high-performance processors and consumes much power in x86 designs. Intel have used two hardware structures to avoid the overheads - first a buffer after the decoders so that small loops that fit this buffer could bypass the decode stages and second a dedicated decoded cache (µop cache) in order to do decode bypassing for larger amounts of code. The µop cache also shortens branch mispredict penalties for jump targets that are stored there.

Intel have a parallel instruction length determination stage before the decoders, AMD use a similar technique in their low power Bobcat core (however as the decoder is only two instructions wide it requires a lot less transistors) and pre-decoded information for Bulldozer family designs. Both techniques require more power than traditional RISC instruction decoders.

One also have to remember that the PPC family is one of the most "un-RISCy" RISC designs and that high performance PPC designs often use both pre-decode information and several pipeline stages for decoding. There are also instructions that (similar to x86 ones) have to be split into more RISCy ones.

@megol

Cortex A9 and A15 also break their instructions into simpler ones, if I'm not mistaken.

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@WolfToTheMoon

Yes but ARM have a lot of things that aren't traditionally RISC :)
Condition codes with optional updating.
Predicated instructions per default.
Barrel shifter before the integer ALU.
Load/store multiple registers.
Address register updates.
Optional 16 bit encodings.
Optional Java acceleration support (not anymore, still exists some remnants IIRC).

Many of those was the reason why an ARM processor could have both compact code and excellent performance without transistors "wasted" on caches. Most of them complicate superscalar and out of order designs though.

Their 64 bit design (AARCH64) is in comparison a relatively boring traditional RISC design

@thread

power.org q4 2012 newsletter online:

https://www.power.org/newsletter/q4-2012-newsletter/#NM2

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retired

I think that it is useless to talk about the new processors until AmigaOS4 will not have SMP and threads support.

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A1200 + (looking for bppc060) + bvppc + Indivision AGA MKII + OS 3.9
A3000 + OS 3.9

@coriolis

I think it's always good to keep an eye on what is going on in PPC world.

SMP/AMB/BMP/someMulticoreSupport is being built in AOS4.2, so it should not be futile to plan HW that would utilize it nicely.

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- KimmoK
// For freedom, for honor, for AMIGA
//
// Thing that I should find more time for: CC64 - 64bit Community Computer?

@KimmoK

Am I really the only one who sees any value in running multiple instances of Linux and AOS4 through the hypervisor of QorIQ?

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This weeks pet peeve:
Using "voltage" instead of "potential", which leads to inventing new words like "amperage" instead of "current" (I, measured in A) or possible "charge" (amperehours, Ah or Coulomb, C). Sometimes I don't even know what people mean.

@olegil

Quote:

Am I really the only one who sees any value in running multiple instances of Linux and AOS4 through the hypervisor of QorIQ?

No.

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Rock lobster bit me. My Workbench has always preferences. X1000 + AmigaOS4.1 FE
"Anyone can build a fast CPU. The trick is to build a fast system." -Seymour Cray

@Tomppeli

Ah. Good. Was starting to wonder

Been looking into the 2041 and they really shrank it one step too far. 28x28 grid of balls in 0.8mm pitch is dang tricky to escape route. So it would have to be micro-via (laser-cut 1 layer at a time instead of the conventional through-board drilled vias). This increases PCB cost and sort of locks one in to a tight partnership with the PCB manufacturer (not so easy to switch later as they might not agree on what's ok to do).

But the world is going towards 0.4mm BGAs, so it's becoming standard procedure anyway.

On second thought, having looked at it again (and routed a little) it looks like it's got so much power and ground compared to the very few signal pins that micro-via might be a bit like hunting moose with ICBM. 10 layers and conventional vias would probably be plenty. I ended up with 10 layers on the P1025 as well, due to a very narrow board, just 70x170mm, with extremely tight DDR3 routing.

anyhoo, bed time

_________________
This weeks pet peeve:
Using "voltage" instead of "potential", which leads to inventing new words like "amperage" instead of "current" (I, measured in A) or possible "charge" (amperehours, Ah or Coulomb, C). Sometimes I don't even know what people mean.

One of the first products that ship with latest generation of Freescale PPC chips:
http://www.cwcdefense.com/products/single-board-computers/3u-ppc-sbc/vpx3-133.html

And about IBM investment in PPC Linux:
"Nvidia's involvement will see it and IBM work together to integrate Nvidia's CUDA GPU technology into Power-based ecosystems."
http://www.v3.co.uk/v3-uk/news/2287420/ibm-google-nvidia-form-openpower-consortium-to-target-data-centres

Would be nice to see PPC chip with integrated Nvidia GPU ....

Last edited by KimmoK on 16-Oct-2013 at 07:46 PM.
Last edited by KimmoK on 16-Oct-2013 at 07:46 PM.

_________________
- KimmoK
// For freedom, for honor, for AMIGA
//
// Thing that I should find more time for: CC64 - 64bit Community Computer?

@KimmoK

Only IBM partnered with nVidia... and there is no space on the POWER8 die for a integrated GPU unit.. hell, they even moved memory controller of the CPU die...

I believe they will probably invest in mostly software/CUDA related issues.

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@WolfToTheMoon

IIRC G5, PA6T, xbox360 CPU, PS3 CPU and PPC476FP are all cut down versions of POWER processor.
Similarly cut down version of POWER8 would give plenty of room for GPU on die.


UPDATE:
Summary of POWER chips:
http://zapt5.staticworld.net/images/article/2013/08/ibm-power8-roadmap-2-100051578-large.png
more details: http://en.wikipedia.org/wiki/IBM_POWER_microprocessors
"POWER8 is a 4 GHz, 12 core processor with 8 hardware threads per core for a total of 96 threads of parallell execution."

I would not mind seeing a single core version with 8 threads @ 5Ghz with some 2MB L2 cache + small OpenGL2.0 caliber GPU. (ok, lets forget those threads for now)


((I wonder why Hyperion guys have not run & shown AOS4 on real IBM POWER computer allready. And There would be a few people willing to get 5Ghz AOS4 machine for ... 5000EUR, just for the kicks?))

Last edited by KimmoK on 17-Oct-2013 at 06:14 AM.
Last edited by KimmoK on 17-Oct-2013 at 06:04 AM.

_________________
- KimmoK
// For freedom, for honor, for AMIGA
//
// Thing that I should find more time for: CC64 - 64bit Community Computer?

@KimmoK

G5 is a cut down POWER.

PA6T was a clean sheet design, no connections to IBM.

XBox CPU is an in-order CPU, no connections to POWER chips.

I don't know what's the story behind CELL, but I rather doubt it had much to do with POWER.

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@WolfToTheMoon

As in finland we would say something like ööö if we have some doubts

http://en.wikipedia.org/wiki/Cell_(microprocessor)

@utri007

Have a Aos 4.1 on cell will be great 8)

_________________
I love Amiga and new hope by AmigaNG
A 500 + ; CDTV; CD32;
PowerMac G5 Quad 8GB,SSD,SSHD,7800gtx,Radeon R5 230 2GB;
MacBook Pro Retina I7 2.3ghz;
#nomorea-eoninmyhome

@tlosm

No it wouldn't...

CELL is very slow for a general computing tasks. Sub AMD Sempron of the day.

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@WolfToTheMoon

I know you would really really like amiga os to go x86, but I don't see that happening.

And actually the CELL is not that slow.

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@Yssing

A CELL at 3.2 GHz is slower than a 1.6 GHz G5 in general computing tasks.

So yeah... as a central CPU unit it would majorly suck for a desktop computer.

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PA6T: "based around the Power architecture, which it has licensed from IBM." so not a cut down precisely, but licenced architecture.

xbox360: "based on IBM PowerPC instruction set architecture, consisting of three independent processor cores on a single die. These cores are slightly modified versions of the PPE in the Cell processor used on the PlayStation 3."

Cell: licenced and "designed over a period of four years, using enhanced versions of the design tools for the POWER4 processor."


etc...
Some POWER cores + GPU is doable but more than Amigans are needed to make it happen.


(single PPE at 3.2Ghz should do ~6000MIPS, so for Amiga apps also that would be ok, if the price is right.)

Last edited by KimmoK on 17-Oct-2013 at 02:08 PM.
Last edited by KimmoK on 17-Oct-2013 at 02:01 PM.

_________________
- KimmoK
// For freedom, for honor, for AMIGA
//
// Thing that I should find more time for: CC64 - 64bit Community Computer?

@KimmoK

Quote:

single PPE at 3.2Ghz should do ~6000MIPS, so for Amiga apps also that would be ok, if the price is right.)

IBM estimated performance of PPU in Cell (as used in PS3) as 423 SpecInt2000. That is probably even slower than PA6T or higher clocked G4.