Yes, if the Arcade board would have been available 3 years ago it could have helped indeed. But today it really makes no sense to think about the Arcade board for us. The NATAMI is bigger and the NATAMI is easier available than the Arcade board.
The Arcade board is a nice development and certainly has its own market. The MiniMig is also a very nice design and has its own market. But the NATAMI is a very different design and has a different goal.
We have some nice FPGA dev toys but for me none of them makes sense to use - only the NATAMI.
Last edited by BigGun on 12-May-2010 at 10:21 PM. Last edited by BigGun on 12-May-2010 at 10:16 PM.
The Natami team have been completely open with people right from the beginning (and how often is that the case in this community?), posted continuous status updates, screenshots, demoed the previous prototype live and now shown a video of the new prototype.
although it's true they answer questions in the natami forums and posted some pictures of new motherboards/cpu modules I didn't notice videos of Natami running software, just remember the old pictures from amiga.org.
Due to the way DDR memory works I think they may be using the rising signal flank of the pulse for custom chip access and the falling one for cpu accesses.
Don't take this as a negative critic, it's just that I had the impression there were not many videos of Natami in action.
@Arko
relax man Tobiflex commented that DDR access was tricky and he is the author of the m68k core for AlteraDE1/DE2 and I think it has been used by Yaqube on fpgaarcade too. I just would like to see more videos of Natami in action to make nicer the wait for it.
@BigGun
remember to show us a video of TBL's "Starstruck" or Elude's "We come in peace" when you have AGA and 060 working with the new design!
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BigGun
Re: Giana Sisters running on Natami Posted on 12-May-2010 23:18:54
Due to the way DDR memory works I think they may be using the rising signal flank of the pulse for custom chip access and the falling one for cpu accesses.
You seem to conceptionally misunderstand how DDR memory is working.
Ill try to explain it with an easy example:
With DDR you send 1 address and then a burst of data belonging to this address will be transmitted. It would similar to like the 68040 or 68060 did burst in their 16byte cache lines.
Typical burst size is 4 words. If your memory interface is 32bit this means every memory access READ or WRITE will transfer 128bit in one go - ALWAYS!
The AMIGA chipset originally was not prepared for bursting. When AGA was developed a short burst of 64bit was added for the Video and Sprite DMA. But bursting and buffering was never added for the Blitter or Audio or Copper or other DMA channels.
Finally now the NATAMI does correct this.
Now all AMIGA DMA is bursting. And the DMA is not only bursting but also doing pipelined burst.
Example of a pipelined burst and "old school" memory interface. Todays memory has a latency of roughly 20 clocks this means if your FPGA clocks with 200 MHz then you "old school" blitter can fetch every 20 clocks a word of 16bit. This give you a blitter bandwidth of 20 MB/sec. Better than old AGA but not very exciting.
Using the same Hardware you could burst every 20 clocks a 28 bit word. To be able to do this you need to add the right buffers to your Blitter. This gives you a bandwidth of 160 MB/sec. That is a lot better isnt it?
Now when your DMA will also proper pipeline the burst also then you can have 5-6 burst in flight in parallel. This will finally you a bandwidth in the order of 800 MB/sec Now we are talking.
The NATAMI did has working AGA already 2 years ago. For those that wondered what was changed / developed since these 2 years. I think you know the difference know.
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BigGun 
Tobiflex commented that DDR access was tricky and he is the author of the m68k core for AlteraDE1/DE2 and I think it has been used by Yaqube on fpgaarcade too. I just would like to see more videos of Natami in action to make nicer the wait for it.
