I’ll kick you off…

Compared to VAX, 68k is a toy!
CISC vs RISC is an irrelevant discussion today.
microkernel vs monolithic equalle so.
Realtime (RT) doesn’t mean what you think it does.
AGA was fine for its time.
And who effin cares about Deluxe Music 2 anyways?

Enjoy!

You’re welcome.

Last edited by kolla on 15-Feb-2025 at 02:34 AM.

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B5D6A1D019D5D45BCC56F4782AC220D8B3E2A6CC

@kolla

This thread has great potential; it would be a shame... if something were to happen to it.

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Indigo 3D Lounge, my second home.
The Illusion of Choice | Am*ga

@kolla

Everyone knows PowerPC is king of the CPU hill!

_________________

@kolla

Z80





Wol..

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It is my conviction that killing under the cloak of war is nothing but an act of murder.~Albert Einstein

kolla Quote:

I’ll kick you off… Compared to VAX, 68k is a toy!

The undisputed all time toy architecture is the 8-bit 6502 family. Jay Miner tried to integrate the 68k Amiga to lower the the cost and David Morse was brought in from Tonka Toys to be CEO of Hi Toro which became Amiga Corporation for marketing it as a toy. Commodore bought the Amiga and failed to continue integrating and enhancing it enough though. They were still using the original mid-1970s NMOS silicon in the mid-1990s when they went bankrupt and failed to produce a CMOS 68k Amiga SoC that internal documents claim would have reduced the price of 68k Amiga hardware by $100 USD in addition to a major performance improvement and AA+ chipset enhancements that could have allowed the 68k Amiga to become the 32-bit embedded SoC of choice for toys. A-EonKit is repeating the Commodore mistake of using 20 year old outdated silicon by using 15 year old outdated PPC SoC silicon. For toys, they are also repeating the mistake of Motorola replacing the number 1 embedded market 32-bit 68k architecture with fat PPC while the number 4 architecture fat ARM swapped to Thumb with the single purpose goal of improving code density using 68k and SuperH tech. The result is that ARM Thumb(-2) is the 32-bit toy architecture even though the 68k is as good as if not a better choice. Code density is close even though the 68k has a narrow advantage, the 68k has a significant performance advantage and Thumb(-2) has an area and power advantage which narrows and may even be lost for power efficiency. The VAX 8-bit variable length encoding is like x86(-64) and the decoding complexity is too high for small cores and embedded use toys. The VAX ISA is more orthogonal than x86 and has 16 GP registers instead of 8 GP registers but the flexibility of the ISA may require more microcode than x86.

kolla Quote:

CISC vs RISC is an irrelevant discussion today.

That is what RISC ISA designers claim before replacing their RISC ISA with a new RISC ISA to compete with CISC ISAs that retain compatibility and baggage. RISC-VI will be the replacement for RISC-V but what will ARM call their 4th RISC ISA do over?

kolla Quote:

microkernel vs monolithic equalle so.

Maybe it does not matter for modern CISC powerhouse CPUs but the kernel may matter for small anemic embedded RISC cores where latency may be increased by large monolithic kernels reducing their realtime capabilities.

kolla Quote:

Realtime (RT) doesn’t mean what you think it does.

Latencies are decreasing as integration improves but jitter is increasing with more levels of cache unless using a MCU with SRAM memory. It really depends on what the application realtime requirements are but apparently I do not understand what that means.

kolla Quote:

AGA was fine for its time.

Barely and for a short time maybe AGA was fine but Moore's Law soon kicked its ass. It did not help that AGA was still 3 chips with 2 being NMOS chips using mid 1970s silicon in the mid 1990s.

kolla Quote:

And who effin cares about Deluxe Music 2 anyways?

The Deluxe Music compatibility test and the Quake performance test are the most important benchmarks for the Hammer benchmark suite.

Was I too serious when answering the questions?

@kolla

Deluxe Music 2 is an Amiga software from EA, an early C= Amiga supporter, and established IFF format on the C= Amiga. Deluxe Music is the midi counterpart of graphics Deluxe Paint.

Deluxe Music Mac version can run on MacOS from ShapeShifter or Fusion.

Quote:

Compared to VAX, 68k is a toy!

That's your argument, not mine.

VAX CISC processor wasn't a mass seller. DEC also sold a 68K display terminal e.g. VAXstation 100.

VAXstation 100 consisted of a desk-side unit housing a Motorola 68000 processor, a dedicated bit blit accelerator built from AMD 2901 logic, and a total of 640KB of RAM (128KB for the CPU, and a 512KB frame buffer. VAXstation 100 was used to create the original X Windows system.


Quote:

AGA was fine for its time.

It was reasonable for it's price. Commodore couldn't produce enough of them.

Last edited by Hammer on 15-Feb-2025 at 09:09 PM.
Last edited by Hammer on 15-Feb-2025 at 09:07 PM.
Last edited by Hammer on 15-Feb-2025 at 09:07 PM.
Last edited by Hammer on 15-Feb-2025 at 08:45 PM.

_________________
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@kolla

I misread the title as the Matthey and Hammer Help Thread.

_________________
Doing stupid things for fun...

Aren't they all ?

@BillE

No they are more "need help" ;)

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Doing stupid things for fun...

@matthey

Quote:

The result is that ARM Thumb(-2) is the 32-bit toy architecture even though the 68k is as good as if not a better choice. Code density is close even though the 68k has a narrow advantage, the 68k has a significant performance advantage and Thumb(-2) has an area and power advantage which narrows and may even be lost for power efficiency. The VAX 8-bit variable length encoding is like x86(-64) and the decoding complexity is too high for small cores and embedded use toys. The VAX ISA is more orthogonal than x86 and has 16 GP registers instead of 8 GP registers but the flexibility of the ISA may require more microcode than x86.

The P5 Pentium era has standardized with FPU. It can transfer data between FPR and GPR without penalty, and it has effectively 16 registers. All Pentium models have FPU as standard.

Like 68040, Motorola couldn't guarantee 68060's FPU existence.

8087 FPU can process INT32 and INT64 in addition to floating point formats which sets the template for Pentium FPU.

PC games like Tomb Raider (1996) used X87 FPU. Core Design started Tomb Raider's development in 1994. Tomb Raider was influenced by 3D texture-mapped Ultima Underworld: The Stygian Abyss (1992) and solid polygon 3D Virtua Fighter (1993).

In 1985, a full VLSI (microprocessor) implementation of the MicroVAX architecture was released with the MicroVAX II's 78032 (or DC333) CPU and 78132 (DC335) FPU. VAX arrived too late in the mass production CPU and FPU market. DEC switched to RISC focus R&D e.g. Alpha.

The Soviet Union state enterprise illegally cloned 78032 as KL1807VM3.
East Germany state enterprise illegally cloned 78032 as U80701.

68000 didn't have FPU until 1984's 68881 release while 8086/8088 had 8087 FPU for IBM's 1981 original PC.

68000 can process up to INT32 while 8087 FPU can process INT32, INT64, FP32, FP64 and FP80. 1985 released Lotus 123 2.0 supported 8087 and 80287 FPUs and solidified IBM's x86-based PC as a business micro-computer platform. MS Excel focused on "next-gen" GUI business software design via 68K MacOS and MS Windows 2.x to unseat high-resolution text UI Lotus 123 establishment.

C64's unit sales were kept up with IBM PC's unit sales up to around 1985.

Like MacOS, Windows 3.0 will use FPU to improve GUI draw performance.
https://imgur.com/a/coprozessoren-f-r-windows-3-1-9ocY2
https://www.vogons.org/viewtopic.php?t=57408


Before Tomb Raider, Core Design released BC Racers (3rd Chuck Rock) in 1994 and didn't port to Amiga CD32. Sega Mega-CD has an extra 12 Mhz 68000 CPU and custom graphics AISC for SNES's Mode 7 texture map effects. BC Racers was released for Sega Mega CD, Sega X32 (SuperH2), 3DO, and MS-DOS PC. Tomb Raider was developed for Sega Saturn (SuperH2, integer only), MS-DOS PC (in 32-bit protected mode with FPU), and PlayStation (MIPS R3000A, integer only) simultaneously.

Running PC's Tomb Raider on 486SX2-66 invokes slow FPU emulation. On the PC, FPU also matters. PC's Tomb Raider 2 has the MMX software renderer.

Last edited by Hammer on 18-Feb-2025 at 12:46 AM.
Last edited by Hammer on 18-Feb-2025 at 12:16 AM.
Last edited by Hammer on 18-Feb-2025 at 12:06 AM.

_________________
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@matthey

Quote:

Barely and for a short time maybe AGA was fine but Moore's Law soon kicked its ass. It did not help that AGA was still 3 chips with 2 being NMOS chips using mid 1970s silicon in the mid 1990s.

Paula's replacement, Mary chip is tied to AAA's Andrea's DMA controller. Mary chip doesn't work with AA's Alice.

Amiga architecture wasn't properly partitioned to separate low-performance chips from high-performance chips.

Commodore couldn't use Mary's improvements for AA Amiga.

Amiga's inherent game console architecture is unsuitable against a rapidly evolving PC's partitioned architecture.

During 1991, Amiga AAA reached alpha state and Amiga AA reached beta state.

AAA Andrea's R&D was slowed down by 2MB Agnus ECS bugs fixing and C65 chipset R&D.
2MB Agnus ECS sets the foundation for AA Alice.

C65 chipset R&D effort should been for the Amiga R&D. During 1987, Henri Rubin was slow to restart next gen R&D for Amiga, hence why CSG's LSI group started the C65 R&D project.

Henri Rubin's R&D approach is reactionary #metoo and focuses on GVP style add-ons R&D business for A2000. Henri Rubin didn't factor in longer lead times for cutting-edge ASIC designs.

Henri Rubin has no experience in CPU R&D, he can't even use a desktop computer.

-----------------

SUN GX's two custom ASICs for 3D acceleration and it was released in 1989.
https://old.hotchips.org/wp-content/uploads/hc_archives/hc01/3_Tue/HC1.S8/HC1.8.2.pdf

The designer for SUN GX later co-founded NVIDIA in 1993.

TEC (transformation engine and cursor) features
* 3D transforms math with 51 MFLOPS FP32, scaling, rotation, translation, and 'etc'. Supports fixed point and floating point formats.
* 212K transistors

FBC (frame buffer controller) features
* 16 ROPS (raster operations),
* Bitbilt with raster operations,
* Antialisaing
* Clipping
* Barrel Shifter
* Context Switchable
* 170K transistors

https://youtu.be/4RQscDJCy4c?t=81
Aviator 1.5.1 running on SunOS 4.1.4 on a Sparcstation 20 with GX+ 3D accelerator.
SUN GX is a quadrilateral polygon fill system like NVIDIA's NV1 project.


https://en.wikipedia.org/wiki/Jensen_Huang

After graduating from college, Huang was a microchip designer in Silicon Valley. He had interviewed for positions at Texas Instruments, Advanced Micro Devices (AMD), and LSI Logic, ultimately choosing the California-based AMD due to already being familiar with the company. He designed AMD microprocessors while simultaneously attending Stanford and raising his two children.

However, when he heard of new chip design processes at LSI Logic, Huang left AMD to assume a role as a technical officer at the LSI Corporation, working under a startup company, Sun Microsystems, where he met engineers Chris Malachowsky and Curtis Priem.

LSI was in contract with Sun Microsystems and had introduced Huang to Malachowsky and Priem, who were working on a new graphics accelerator card. While the three produced the card's manufacturing process, the relationship between Malachowsky and Priem became strained as the two disputed the chip's design, leading to infighting; according to Malachowsky, they "broke every tool that LSI Logic had in their standard portfolio".

In 1989, Huang, Malachowsky, and Priem finalized the accelerator, which they called the "GX graphics engine". GX was a widespread financial success; the sales of the graphics engine contributed to Sun Microsystem's revenue increasing from $262 million in 1987 to $656 million in 1990, and Huang was promoted to be the director of LSI's CoreWare, a division that manufactured chips for hardware vendors

(skip)

Although he left LSI, Huang remained in good standing with the company and was able to secure funding for Nvidia from LSI's CEO, Wilfred Corrigan, who introduced Huang to venture capitalist Don Valentine. Valentine, the leader of Sequoia Capital, chose to invest in Nvidia, as did Sutter Hill Ventures. The funding enabled Nvidia to begin development efforts toward its first chip and to begin paying wages for its employees.



LSI's CoreWare was instrumental for Sony's PlayStation. Sony PlayStation was influenced by SGI (e.g. MIPS R3000A CPU, triangle polygon system) and Evans & Sutherland's texture mapper technology via Namco System 22 and Ridge Racer game use case.

In 1989, ex-original Amiga engineers started to design 3DO with texture-mapped quadrilateral 3D system being the primary target use case. 3DO engineers switched to a triangle polygon system with 3DO M2 that was completed in 1995 and IP was sold to Panasonic.


------------------------

Sega has access to Lockheed Martin's Real3D texture mapper technology which was later purchased by Intel in 1999.

For the Sega Saturn project, 68030 was considered before switching to a dual SuperH2 config. 68EC040/68LC040's price is too costly for Sega.

Quote:

For toys, they are also repeating the mistake of Motorola replacing the number 1 embedded market 32-bit 68k architecture with fat PPC while the number 4 architecture fat ARM swapped to Thumb with the single purpose goal of improving code density using 68k and SuperH tech

PowerPC ISA had 16-bit ISA extensions known as Book VLE (Variable Length Encoded Instruction Architecture). This extension availability is not guaranteed for larger PowerPC CPU cores.

Freescale PowerPC e200 series has Book VLE.

PPC e200z0 has no MMU and no FPU i.e. "EC".
PPC e200z1 has 16 entry MMU, no FPU i.e. "LC".
PPC e200z3 has 16 entry MMU, FPU, and SIMD FP, 32-bit PPC Book E ISA, and 16-bit PPC VLE ISA.
PPC e200z4 has dual issue pipelines, 16 entry MMU, FPU, and SIMD.
PPC e200z6 improved 32 entry MMU, 64-bit bus, longer 7-stage pipeline, backward single issue, LOL.
PPC e200z7 has longer dual issue 10-stage pipelines, 32 entry MMU.

Freescale PowerPC e200 addressed the code density issue and terminated ColdFire/68K into oblivion. STM is the second source for the PowerPC e200 series.

For development, QEmu has PPC Book VLE emulation support.

Last edited by Hammer on 20-Feb-2025 at 01:11 AM.
Last edited by Hammer on 18-Feb-2025 at 05:59 AM.
Last edited by Hammer on 18-Feb-2025 at 05:46 AM.
Last edited by Hammer on 18-Feb-2025 at 05:41 AM.

_________________
Amiga 1200 (rev 1D1, KS 3.2, PiStorm32/RPi CM4/Emu68)
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Hammer Quote:

VAX CISC processor wasn't a mass seller. DEC also sold a 68K display terminal e.g. VAXstation 100. VAXstation 100 consisted of a desk-side unit housing a Motorola 68000 processor, a dedicated bit blit accelerator built from AMD 2901 logic, and a total of 640KB of RAM (128KB for the CPU, and a 512KB frame buffer. VAXstation 100 was used to create the original X Windows system.

VAX was the 32-bit successor of the very successful 16-bit PDP-11 which the 68k and NS32k are heavily influenced by. DEC would have been better off enhancing the PDP-11 instead of creating the VAX which was a move in the wrong direction followed by the Alpha which was a move in another wrong direction. DEC had made some mistakes with the PDP-11 like mixed endian issues which the 68k fixed while providing the most enhancement to become a 32-bit ISA. The NS32k is perhaps a closer and cleaner upgrade of the PDP-11 to 32-bit using little endian but datatypes in the 16-bit variable length instructions mysteriously use big endian.

Hammer Quote:

The P5 Pentium era has standardized with FPU. It can transfer data between FPR and GPR without penalty, and it has effectively 16 registers. All Pentium models have FPU as standard. Like 68040, Motorola couldn't guarantee 68060's FPU existence. 8087 FPU can process INT32 and INT64 in addition to floating point formats which sets the template for Pentium FPU.

Each x86 FPU instruction can access the top of the FPU stack registers which is like having one FPU register. Accessing cached memory can be better than accessing the FPU registers other than the top of stack register. Maybe using the GPR registers looks good compared to using the gimp FPU stack registers but is likely not free on all implementations. It is far from free using the 68060 FPU where accessing cached memory is often preferable.

A FPU pipeline is generally deeper and wider than an integer pipeline so is higher latency and more costly for performing integer calculations. Also, FPU code is generally larger than integer code, especially with the x86 FPU which requires an extra FPU instruction to access any other FPU stack register than the top one. There is a reason the bad x86 FPU design was deprecated.

Hammer Quote:

PowerPC ISA had 16-bit ISA extensions known as Book VLE (Variable Length Encoded Instruction Architecture). This extension availability is not guaranteed for larger PowerPC CPU cores. ... Freescale PowerPC e200 addressed the code density issue and terminated ColdFire/68K into oblivion. STM is the second source for the PowerPC e200 series.

The Freescale PPC VLE extension was late in the life of PPC and poorly supported. VLE is a replacement PPC ISA encoding that is incompatible with the original PPC ISA encoding due to encoding addresses and displacements not having the lower two bits. IBM had earlier chosen a different approach to compression called CodePack. ColdFire and 68k have a standard 16-bit variable length encoding from inception which is more efficient than adding compressed encodings, especially in the case of PPC which was challenging. PPC VLE did not kill ColdFire and the 68k which is a ridiculous claim. Motorola/Freescale killed the 68k for political reasons and to improve economies of scale for PPC which they bet the farm on. ColdFire died because it was not 68k compatible and was not scalable enough after castrating the 68k to the very low end embedded market below where fat PPC could scale and where ARM Thumb small area and power cores competed against the better performance of ColdFire and won. If ColdFire had been designed to support 64-bit, it may very well be alive today but any upgradability was seen as a threat to PPC.

@matthey

Quote:

VAX was the 32-bit successor of the very successful 16-bit PDP-11 which the 68k and NS32k are heavily influenced by. DEC would have been better off enhancing the PDP-11 instead of creating the VAX which was a move in the wrong direction followed by the Alpha which was a move in another wrong direction. DEC had made some mistakes with the PDP-11 like mixed endian issues which the 68k fixed while providing the most enhancement to become a 32-bit ISA. The NS32k is perhaps a closer and cleaner upgrade of the PDP-11 to 32-bit using little endian but datatypes in the 16-bit variable length instructions mysteriously use big endian.

DEC's VAX integration into a single CPU chip package is late.

Apple's 68K Macintosh platform has no problems beating DEC VAX on desktop unit sales.

MacOS's human-friendly stable high-resolution GUI and "next-gen" GUI business software for the win.

According to the Atari ST designer, the NS32K has performance issues, hence the 68000 selection.

Quote:

Each x86 FPU instruction can access the top of the FPU stack registers which is like having one FPU register.

The x87 registers form an eight-level deep non-strict stack structure ranging from ST(0) to ST(7) with registers that can be directly accessed by either operand, using an offset relative to the top, as well as pushed and popped.

The non-strict stack model also allows binary operations to use ST(0) together with a direct memory operand or with an explicitly specified stack register, ST(x), in a role similar to a traditional accumulator (a combined destination and left operand). This can also be reversed on an instruction-by-instruction basis with ST(0) as the unmodified operand and ST(x) as the destination. Furthermore, the contents in ST(0) can be exchanged with another stack register using an instruction called FXCH ST(x).

These properties make the x87 stack usable as seven freely addressable registers plus a dedicated accumulator (or as seven independent accumulators). This is applicable on superscalar x86 processors (such as the Pentium of 1993 and later), where these exchange instructions are optimized down to a zero clock penalty by using one of the integer paths for FXCH ST(x) in parallel with the FPU instruction.

From 1997, AMD 3DNow removes the stack problem on X87 registers. Intel added 8 XMM registers.

68060 couldn't guarantee FPU's existence.

For AMD K5 (from March 1996):
branch prediction,
16 bytes per cycle from the L1 instruction cache,
4 hardware decoders,
1 microcode decoder
16 entry reorder buffer,
5 ports for branch, ALU-0, ALU-1, FPU, load/store
6 stage pipeline
Recycles existing Socket 7. Quake blunted K5's integer advantage.
Started from 75 Mhz and 90 Mhz for K5 model 0. In June 1996, a 100Mhz version was released. 133Mhz model was released in 1997.

For AMD K6 (from April 1997):
16 bytes per cycle from L1 instruction cache,
2 short hardware decoders,
1 long decoder,
1 microcode decoder,
24 entry reorder buffer,
6 ports for integer X/MMX ALU, integer Y/MMX ALU, floats, load/AGU, store/AGU, branch,
Recycles existing Socket 7.
From April 1997, 166 Mhz, 200 Mhz, and 233 Mhz was released.

Pentium Pro (P6) was released in 1995 while Amiga's 1st 68060 experience started in 1995 via Phase 5. Escom/QuikPak's A4000T/060 @ 50Mhz started in 1996.

With TF1260 with 100Mhz support, I investigated rev 1 68060's 50Mhz rated clock speed potential and reached 62.5Mhz stable, and 74 Mhz resulted in a lock-up. 68060 needs additional work to reach higher speeds. I have 68LC060 rev 4 (74 Mhz) and 68060 rev 1 (62.5Mhz).

System integration pace is slower on 68K world while Pentium system integration is faster since Intel designs reference PC motherboard designs for Taiwanese PC motherboard manufacturers to copy and paste.

During the 486 release window, CPU release, and PC system offerings (for loyal Intel partners) occurred within the same year which is not the case for 68040.

Commodore's Amiga engineers completed the 68040 with L2 cache accelerator card for A3000's 1990 demo and it was cancelled by management. The magazine reviews criticized the A3000's aging 68030-25 CPU.

Motorola sent the newly minted 68040s to Commodore in the hopes that the major 68040 system would get out of the door ASAP.

68040 was missing in action in partly 1989, the entire 1990, and partly in 1991 which is about two years. Due to missing in action issue, Commodore failed to attract business customers who wanted 4th generation CPU power.

From MIPS R3000's June 1988 introduction, 68K wasn't performance competitive until sometime in 1991. Intel released 486 in June 1989 with the 1st 486 PC system being released within the same year for Xmas Q4 1989. Intel's counterpunch against MIPS R3000 is 1 year.

By 1992 year, Intel revenues are dominated by the 486 CPU sales.

Amiga engineers aimed for the 1990 A3000 with 68040 before Apple. AA3000plus/040 and AA3000plus/030 in Q4 1991. AA3000plus addressed magazine reviews' criticism about lacking 256 color display. AGA's 256 color 640x480p has SVGA's entry point on paper.

Jeff Frank argued for placing the Amiga for the low end while PCs have mid to high end. I extremely dislike Jeff Frank. Jeff Frank of the Commodore PC division is the person who executed Bill Sydnes' directives.

Without AGA, A3000T/040 with ECS is nearly pointless. A2410's 256-color tokenism is useless for general-purpose Amiga applications.

I experienced a fast 68040 with A500 full ECS via PiStorm-Emu68 (using some of the turtle mode features). This is to fake PPS (Progressive Peripherals & Software)'s 68040-28 or 68040-33 accelerator for A500 "what if" experience. ECS is too crap against ET4000AX.

Apple released the Macintosh Quadra 700 (with 68040-25) in October 1991.

My A3000/030-25 is usually faking a Macintosh 030 via AMax-II and Shapeshifter (1995).
I revisit Shapeshifter for my A1200's TF1260 and PiStorm32-Emu68.


Quote:

The Freescale PPC VLE extension was late in the life of PPC and poorly supported. VLE is a replacement PPC ISA encoding that is incompatible with the original PPC ISA encoding due to encoding addresses and displacements not having the lower two bits. IBM had earlier chosen a different approach to compression called CodePack. ColdFire and 68k have a standard 16-bit variable length encoding from inception which is more efficient than adding compressed encodings, especially in the case of PPC which was challenging. PPC VLE did not kill ColdFire and the 68k which is a ridiculous claim.

For microcontroller markets, PowerPC VLE/PowerPC e200 is supported by STMicro and NXP.

ColdFire V5 was the last major core evolution. Hitachi SuperH's 16-bit fixed length instruction exited patent protection; hence Freescale was free to add a 16-bit fixed length LE extension for PPC.

NXP licensed 68020, 68030, 68040 68882 FPU, and 68360 (68020-like CPU32) to Rochester Electronics.

After the legal battle, Hitachi and Freescale's relationship wasn't good. Hitachi is a legal landmine.

Hitachi owned a 16-bit fix-length instruction-related patent and ARM licensed it for 16-bit fixed-length Thumb extension.

Since Motorola/Freescale didn't respect 68K's legacy as a boat anchor, their system integration customers looked elsewhere.

Quote:

Motorola/Freescale killed the 68k for political reasons and to improve economies of scale for PPC which they bet the farm on. ColdFire died because it was not 68k compatible and was not scalable enough after castrating the 68k to the very low end embedded market below where fat PPC could scale and where ARM Thumb small area and power cores competed against the better performance of ColdFire and won. If ColdFire had been designed to support 64-bit, it may very well be alive today but any upgradability was seen as a threat to PPC.

Motorola's largest desktop customer, Apple wanted to move into RISC. Apple invested in MC88000 and its 60x bus before switching to PowerPC. It was Apple who pushed PPC for Motorola. Motorola's PPC 601 has 60x bus support.

Unlike Apple, Commodore wasn't able to grow Amiga's business desktop customers, hence Commodore's "performance without the price" target market wouldn't be a Motorola solution.

Steve Jobs had NeXTSTEP 68K and X86 builds, hence He has no loyalty towards CPU ISA.

Ex-original Amiga engineers from 3DO selected ARM60 @ 12.5 Mhz to 20 Mhz for the original 3DO and IBM PowerPC 602 @ 66Mhz for 3DO M2.

3DO has ARM60 @ 12.5 Mhz or 20 Mhz and MADAM's custom matrix co-processor @ 25Mhz

3DO M2 has dual IBM PowerPC 602 (1 million transistors) @ 66Mhz with each having an FMA3 FP32 unit. 3DO M2's dual CPU is a master/slave design like Sega Saturn's dual SuperH2. To reduce cost, PowerPC 602's 64-bit bus is multiplex between address and 64-bit data mode transfers, and its FPU was cut down towards FP32 hardware.

For similar performance during 1993, MC68030 @ 50 Mhz wouldn't match ARM60's low price.

Amiga Hombre's PA-RISC clone has custom SIMD and Commodore was looking at licensing an existing PA-RISC core design. Amiga Hombre's two-chip solution has a 1 million transistors budget like Sony's PS1.

Fit your pro-68K argument on Amiga Hombre's 1 million transistors budget.

Last edited by Hammer on 20-Feb-2025 at 01:03 AM.
Last edited by Hammer on 19-Feb-2025 at 04:53 AM.
Last edited by Hammer on 19-Feb-2025 at 04:38 AM.
Last edited by Hammer on 19-Feb-2025 at 03:47 AM.
Last edited by Hammer on 19-Feb-2025 at 03:41 AM.

_________________
Amiga 1200 (rev 1D1, KS 3.2, PiStorm32/RPi CM4/Emu68)
Amiga 500 (rev 6A, ECS, KS 3.2, PiStorm/RPi 4B/Emu68)
Ryzen 9 7950X, DDR5-6000 64 GB RAM, GeForce RTX 4080 16 GB

@matthey

The initial BOM costings for the original Xbox

https://www.neogaf.com/threads/3do-mx-chipset-the-technology-nintendo-almost-used-in-an-n64-successor-for-1999.350196/#post-14521193

Brown said the goals were to make money, expand Microsoft's technology into the living room, and create the perception that Microsoft was leading the
charge in the new era of consumer appliances. The initial cost estimate was for a machine with a bill of materials (engineering talk for cost) of $303. That
machine would debut in the fall of 2000 and use a $20 microprocessor running at 350 megahertz from Advanced Micro Devices. The machine would also have
a $55 hard disk drive with two gigabytes of storage, a $27 DVD drive to play movies, a $35 graphics chip, $25 worth of memory chips, and a collection of
other standard parts like a motherboard, and power supply. Over time, these prices would decline.


$20 Intel-compatible microprocessor and a $30 graphics chip from Nvidia. The highest-priced item on the list of materials was $40 for memory chips. But the
rest of the bill of materials was complete, down to $2.14 for the cables and $4.85 for screws


Xbox's BOM cost parameters are close to mainstream Amiga AGA.


https://forum.beyond3d.com/threads/og-xbox-was-planned-to-launch-with-an-amd-cpu-until-last-minute.62562/#post-2225089
Xbox's CPU increased to K7 Duron level. AMD 760 and so nForce/XBox is mostly an AMD chipset that NVidia bought the rights to modify.

The AMD and nForce AMD IDE controllers are fully compatible. (Linux kernel: "AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04 IDE driver for Linux." [12])
The I2C/SMBus controller on the nForce is fully AMD-756/766/68 compatible. [13]
The audio controller is i810 compatible - as is the audio controller of the AMD-768 and the AMD-8111.
The nForce and AMD-768 modems are compatible.
At least one register ("VGA_en") in the nForce PCI-to-AGP bridge is compatible with the AMD chipset (AMD-761, 24081.pdf, page 136).
The nForce uses HyperTransport.


NVIDIA's nForce is mostly from AMD 760 IP and SoundStorm IP from Motorola 56300 based DSP IP.

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Amiga 1200 (rev 1D1, KS 3.2, PiStorm32/RPi CM4/Emu68)
Amiga 500 (rev 6A, ECS, KS 3.2, PiStorm/RPi 4B/Emu68)
Ryzen 9 7950X, DDR5-6000 64 GB RAM, GeForce RTX 4080 16 GB