@thread

https://antmicro.com/blog/2020/07/antmicro-joins-openpower-qna/

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@matthey

Yes, this IS the Power thread, not the ARM thread or the RISC-V thread.

And btw, I can't find many RISC-V boards that are suited to desktop use (actually, basically none), and the few that are are ludicrously high priced.

ARM's cheap, but most boards lack expansion slots.

130nm isn't that bad a process, but the 10mm die size is very limiting.

Quote:

arthoropod wrote: Yes, this IS the Power thread, not the ARM thread or the RISC-V thread. And btw, I can't find many RISC-V boards that are suited to desktop use (actually, basically none), and the few that are are ludicrously high priced. ARM's cheap, but most boards lack expansion slots.

It's important to pay attention to the competition as tech can change quickly. RISC-V has a lot of maturing to do but the availability of open cores by multiple developers is accelerating progress. The RISC-V ISA may lack the performance necessary for high end performance so is unlikely to be a threat to POWER for a long time, if ever. ARM AArch64 is still relatively new but processor designs are maturing quickly and the ISA is likely to provide better performance than RISC-V. While ARM cores are not open cores, licenses are affordable and reference cores are available to accelerate development. There are multiple developers developing cores for server and mid to high performance chips which threatens POWER and even x86_64. IBM is the only developer of POWER cores that I know of while now standardized ARM AArch64 and x86_64 chips have second or multiple suppliers. Would IBM have chosen the 8088 for the PC without AMD as a second source supplier yet expects customers to trust them as the only source of POWER? Is the power savings of POWER in the server market enough to justify the higher costs of sole development and margins IBM expects?

You probably want POWER on the desktop but the cost and high power requirements will probably limit penetration down into that market. I expect ARM designs have a better chance to move up into that market. Apple ARM desktop designs should have expansion and even with the Apple tax should be cheaper and more practical than any POWER desktop system.

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130nm isn't that bad a process, but the 10mm die size is very limiting.

If you just want a custom chip that is cheaper than an FPGA in quantity then 130nm is fine. If you care at all about performance and/or power then choosing a smaller process is worth considering. Too bad they don't have an option to pay the difference from 130nm to the process desired. The die area restriction wouldn't be so bad after a few die shrinks.

Intel announced today that their 7nm process will be delayed another 6 months and that they may use other companies to fab some of their chips. It's getting more and more impractical for chips to go smaller. I expect it is just a matter of time until other fab companies start to have similar problems going smaller. The playing field is slowly leveling and efficiency is becoming important again. POWER and x86_64 have little room to improve while competitors may find advantages and niches.

@all

IBM announces Power10:

https://newsroom.ibm.com/2020-08-17-IBM-Reveals-Next-Generation-IBM-POWER10-Processor

https://www.anandtech.com/show/15985/hot-chips-2020-live-blog-ibms-power10-processor-on-samsung-7nm-1000am-pt

@bennymee

cool PPC lives on yet again eh

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klx300r wrote: cool PPC lives on yet again eh

PPC is dead and the differences with POWER are growing.

POWER has a variable length encoding now with the addition of a prefix. There were 88 new instructions added which use the new 64 bit long instruction encoding with prefix (more instructions than the 68000). So much for the Reduced Instruction Set of RISC. Predecode is between the L2 cache and the L1 ICache implying the internal (and L1 ICache) encoding is different than the POWER ISA. POWER10 is looking more like CISC except without the good code density (notice the POWER10 L1 ICache is 50% larger while the L1 DCache stayed the same size). The only RISC philosophys left are load/store memory accesses and reduced addressing modes which both reduce performance and increase code size. ARM AArch64 added CISC like addressing modes but ignored the benefits of variable length encodings. RISC-V saw the benefits of variable length encodings but ignored more powerful addressing modes. POWER, ARM and RISC-V all ignored the benefits of reg-mem accesses so x86_64 micro-ops with a memory access plus operation outperforms RISC processor micro-ops. POWER and x86_64 have more in common now. They both manage to use a variable length encoding to enlarge code sizes rather than reduce them.

Last edited by matthey on 18-Aug-2020 at 06:46 PM.
Last edited by matthey on 18-Aug-2020 at 03:15 AM.

@bennymee

You beat me posting this news

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@matthey

Quote:

PPC is dead

Maybe.

Byte magazine pronounced Unix dead several times in the late eighties and nineties, and yet it lingers on to this day, although now mostly subsumed by Linux.

PPC could have a long tail.

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@bison

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Byte magazine pronounced Unix dead several times in the late eighties and nineties, and yet it lingers on to this day, although now mostly subsumed by Linux.

Linux Is Not UniX....




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PPC could have a long tail.

Power still haves it's niche uses cases and can't see that chaning but it should tell you something that even PPC CPU vendors have given up development nearly decade ago.

@Rose

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Linux Is Not UniX....

While you're at it, you should tell me that Linux is a kernel, not an OS.

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bison wrote: Byte magazine pronounced Unix dead several times in the late eighties and nineties, and yet it lingers on to this day, although now mostly subsumed by Linux.

Unix was supposed to fix that.

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PPC could have a long tail.

I googled it.

Q: Is PowerPC dead?
A: PowerPC is a dead architecture which is no longer in active development because the AIM alliance no longer exists. You might be thinking of the IBM POWER ISA which was derived from PowerPC. Processors using that ISA are still being designed by IBM and are manufactured by GlobalFoundries or Samsung.

Q: Why did PowerPC fail?
A: PowerPC failed because its vendors hubris. They thought that because their cpu's were based on high end server parts that everyone would jump on the bandwagon without them needing to invest heavily in them. Everyone also thought that the x86 was nearing its' EOL and RISC was the future.

Q: Is Unix dead?
A: Unix's slow decline
“No one markets Unix any more, it's kind of a dead term. It's still around, it's just not built around anyone's strategy for high-end innovation. There is no future, and it's not because there's anything innately wrong with it, it's just that anything innovative is going to the cloud.”

Q: Is Amiga dead?
A: The Amiga died because Commodore denied it growth, support or even respect. ... A group of refugees from companies such as Atari designed the Amiga, and then, needing money for marketing, sold it to Commodore.

Q: Who owns Amiga now?
A: Mike Battilana
On 1 February 2019, Amiga Inc. transferred all Amiga-related rights to C-A Acquisition Corporation owned by Mike Battilana (director of Cloanto, company behind the Amiga Forever emulation package), later renamed to Amiga Corporation.

The great and POWERful AI has spoken. Ignore the cloud bias behind the curtain. Concentrate on the POWER accelerated AI.

POWER ISA v3.1 at the following link.

https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0

Wow! POWER10 is fat! There are something like 34 instruction formats and 145 instruction field types. I stopped trying to count the number of instructions but it is *many* hundreds for sure. I expect the number of instructions is in the 500+ range. For perspective, the 68000 had something like 77 instructions. I can't imagine the jobs of verifying, testing and compiler support for this CPU.

Wikipedia gives the following definition for RISC.

"A reduced instruction set computer, or RISC, is a computer with a small, highly optimized set of instructions, rather than the more specialized set often found in other types of architecture, such as in a complex instruction set computer (CISC). The main distinguishing feature of RISC architecture is that the instruction set is optimized with a large number of registers and a highly regular instruction pipeline, allowing a low number of clock cycles per instruction (CPI). Another common RISC feature is the load/store architecture, in which memory is accessed through specific instructions rather than as a part of most instructions in the set."

Is POWER10 a Reduced Instruction Set Computer anymore?

@matthey

Power10 is the base of next generations high end cpus.
It’s ISA expansion takes advantages of latest GPU and AI trends, even security has grown.. now it can address 8 threads per core.
It’s not a risc and it’s not a cisc, but completely a new flavour of cpu.
Complexity is not changed a lot, leaving existing few addressing modes and adding some new instruction to complete ISA.
Instead being based on a 7nm fab process they chosen to double icache.
It’s a good point for compilers developers, and could be relatively simple add new instructions and take full advantage in few times.

It’s targeted to high end supercomputer world, maybe in combination with latest gpgpu nvidia chips.
..don’t aspect any sort of desktop or workstation machine.. it’s a different market.

Maybe one day there will be a cut off version for embedded market that could be reused for amiga hardware.. maybe in a very far future..

Last edited by Fl@sh on 19-Aug-2020 at 05:49 AM.

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@bison

very long tail

http://bgafc.t-hosting.hu/oses4ppc.php

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Quote:

Fl@sh wrote: Power10 is the base of next generations high end cpus. It’s ISA expansion takes advantages of latest GPU and AI trends, even security has grown.. now it can address 8 threads per core. It’s not a risc and it’s not a cisc, but completely a new flavour of cpu. Complexity is not changed a lot, leaving existing few addressing modes and adding some new instruction to complete ISA. Instead being based on a 7nm fab process they chosen to double icache. It’s a good point for compilers developers, and could be relatively simple add new instructions and take full advantage in few times.

I liked what IBM had done with the POWER9 which made it a more practical CPU. They shortened the pipeline by 5 stages and halved the L1 DCache (load-use penalties and deep pipeline refills really do affect performance). They supported cheaper commodity memory and modular hardware through high speed buses with cache coherency of virtual addresses and minimal latency (IOMMU and ccNUMA?). The instructions and datatype support added were also practical. POWER9 became practical enough for even high end desktops. What went wrong that persuaded them to change direction and add massive parallel performance into the CPU with POWER10?

1) PPC died so there was practically no market for high end PPC/POWER desktops/workstations. If IBM had been many years earlier with this philosophy, POWER could have been the high end option for PPC.
2) Economies of scale could not be leveraged enough selling into one market where x86_64 has 2 markets (servers and desktops) and shares development costs. Also IBM expects high margins.
3) Modularity allowed specialized processors to reduce the need for POWER hardware nodes. Reducing the number of POWER CPUs sold increases costs. One of the biggest culprits is Nvidia GPU parallel processing including their AI acceleration. Nvidia describes in detail at the following link how to save money with Nvidia GPUs by decreasing the number of POWER nodes.

https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/tesla-product-literature/sc18-tesla-democratization-tech-overview-r4-web.pdf

POWER10 brings the massive parallel processing back into the CPU which threatens Nvidia's growing GPU market for servers. This may explain why Nvidia wants ARM. Nvidia would be able to provide their own servers with their low power VLIW ARM cores and Nvidia GPUs.

Quote:

It’s targeted to high end supercomputer world, maybe in combination with latest gpgpu nvidia chips. ..don’t aspect any sort of desktop or workstation machine.. it’s a different market. Maybe one day there will be a cut off version for embedded market that could be reused for amiga hardware.. maybe in a very far future..

I believe you are correct about POWER10 targeting except without the Nvidia GPUs which are decreasing POWER hardware sales. Bigger servers are often just many server CPUs connected together without GPUs, except more recently some have GPUs attached for massive parallel processing workloads instead of display.

It would be difficult for POWER to go back to more practical processors which could be used in high end desktops. They gave up on that philosophy and moved on to much bigger CPUs. POWER is NUMA where embedded would prefer the more consistent, predictable and lower latency UMA or hUMA/HSA with a CPU+GPU SoC for display and/or parallel processing. Embedded is doing lightweight AI now too. One application is edge of network computing AI to reduce the massive amount of data coming in from IoT.

@matthey

Quote:

Unix was supposed to fix that.

I think Jay said that *before* Byte pronounced Unix dead the first time. I could be wrong. He at least said it before it died the second time.

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@thread

Power 10 is impressive!

https://www.enterpriseai.news/2020/08/18/ibm-debuts-power10-touts-new-memory-scheme-security-and-inferencing/

Last edited by AmigaBlitter on 21-Aug-2020 at 02:49 PM.

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@thread

https://libre-soc.org/

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AmigaBlitter wrote:
@thread

Power 10 is impressive!

https://www.enterpriseai.news/2020/08/18/ibm-debuts-power10-touts-new-memory-scheme-security-and-inferencing/[/quote]

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c64-2sids, A1000, A1200T-060@50(finally working!),A4000-CSMKIII
! My Master Miggies- Amiga 1000 & AmigaOne X1000 !
mancave-ramblings
X1000 I BELIEVE

@thread


Power9 Soc first boot:

https://twitter.com/lkcl/status/1301468211024723968


Can the Vampire team start working on a Power9 FPGA core?

Just asking

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