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cdimauro 
Re: PowerPC notebook - Status update
Posted on 6-Jun-2015 9:30:05
#41 ]
Elite Member
Joined: 29-Oct-2012
Posts: 2794
From: Germany

@pavlor

Quote:

pavlor wrote:
@cdimauro

Quote:
being produced today.

Quote:
iBook and PowerBook


I don΄t think this is right anwer to scabit΄s question.

I don't think that his question is right with the my previous statement:

"there are already PowerPC laptops."

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pavlor 
Re: PowerPC notebook - Status update
Posted on 6-Jun-2015 9:44:22
#42 ]
Elite Member
Joined: 10-Jul-2005
Posts: 9373
From: Unknown

@cdimauro

Quote:
I don't think that his question is right with the my previous statement:


So, you answered to yourself?

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cdimauro 
Re: PowerPC notebook - Status update
Posted on 6-Jun-2015 10:01:34
#43 ]
Elite Member
Joined: 29-Oct-2012
Posts: 2794
From: Germany

@pavlor: I just reported a fact, to everyone which wants to read it.

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Hypex 
Re: PowerPC notebook - Status update
Posted on 6-Jun-2015 17:41:43
#44 ]
Elite Member
Joined: 6-May-2007
Posts: 10718
From: Greensborough, Australia

@cdimauro

Those are old hat machines. This is obviously a new development. And what we are talking about is a new PPC laptop which you knew of.

Anyway I've got a few PPC laptops around here and they all have something broken. The one that works has a small screen and no Radeon so MorphOS is out. If OS4 is only worth the value of old hardware it can possibly run on there's not much point developing it futher.

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cdimauro 
Re: PowerPC notebook - Status update
Posted on 6-Jun-2015 17:50:31
#45 ]
Elite Member
Joined: 29-Oct-2012
Posts: 2794
From: Germany

@Hypex: the problem is that it's very difficult to produce a new PowerPC laptop, and at the end it doesn't have a super-mega powerful CPU, because you have very limited choice.

Instead Apple's laptops are already existing, produced in millions, and with a good CPU which is quite comparable (if not even better sometimes).

You only need to port OS4, which isn't a "mission: impossible". The MorphOS team already did it, and anyway even for a new laptop OS4 has to be ported...

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pavlor 
Re: PowerPC notebook - Status update
Posted on 6-Jun-2015 18:42:54
#46 ]
Elite Member
Joined: 10-Jul-2005
Posts: 9373
From: Unknown

@cdimauro

Quote:
Instead Apple's laptops are already existing, produced in millions, and with a good CPU which is quite comparable (if not even better sometimes).


Better? In what aspect. T2080 seems to be far more powerful than 7447A:

MHz
T2080: up to 1800 MHz
7447A: 1666 MHz

DMIPS
T2080: 3.3 DMIPS/MHz
7447A: 2.3 DMIPS/MHz

CPU Cache
T2080: L1: 32 I + 32 D kB, L2: 2 MB, L3 (platform cache): 512 kB
7447A: L1: 32 I + 32 D kB, L2: 512 kB

etc.

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cdimauro 
Re: PowerPC notebook - Status update
Posted on 6-Jun-2015 19:43:06
#47 ]
Elite Member
Joined: 29-Oct-2012
Posts: 2794
From: Germany

@pavlor

Quote:

pavlor wrote:
@cdimauro

Quote:
Instead Apple's laptops are already existing, produced in millions, and with a good CPU which is quite comparable (if not even better sometimes).


Better? In what aspect. T2080 seems to be far more powerful than 7447A:

MHz
T2080: up to 1800 MHz
7447A: 1666 MHz

DMIPS
T2080: 3.3 DMIPS/MHz
7447A: 2.3 DMIPS/MHz

CPU Cache
T2080: L1: 32 I + 32 D kB, L2: 2 MB, L3 (platform cache): 512 kB
7447A: L1: 32 I + 32 D kB, L2: 512 kB

etc.

MIPS. Again. I don't like such kind of unit of measure, which I consider misleading, as I stated in another thread.

Consider that the T2080 is able to decode and execute 2 instructions per clock cycle, whereas the G4 can decode and execute 4 (of which one should be a branch).

So, it's better to take a look at benchmarks with real applications.

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pavlor 
Re: PowerPC notebook - Status update
Posted on 6-Jun-2015 20:27:16
#48 ]
Elite Member
Joined: 10-Jul-2005
Posts: 9373
From: Unknown

@cdimauro

Quote:
So, it's better to take a look at benchmarks with real applications.


Of course. T4240 scored in single-core SpecInt2006 benchmark result of 6.86 (at 1666 MHz). There aren΄t comparable results for G4 CPUs, but knowing their SpecInt2000 numbers, I don΄t think they would score better.

Edit: About e6500 core (e6500 core reference manual, p. 1-1)

The e6500 core is a multi-threaded superscalar processor that can decode two instructions and complete two instructions per thread per clock cycle. Instructions complete in order, but can execute out of order. Execution results are available to subsequent instructions in the same thread through the rename buffers, but those results are recorded into architected registers in program order, maintaining a precise exception model.

The processor core integrates the following execution units:
• Four simple instruction units (SFX0 and SFX1 per thread)
• One multiple-cycle instruction unit (MU)
• Two branch units (BU, one per thread)
• One floating-point unit (FPU)
• One AltiVec unit (VSFX, VCFX, VFPU, VPERM)
• Two load/store units (LSUs, one per thread).
— The LSUs support 64-bit integer and floating-point operands and 128-bit vector operands for AltiVec operations.

About e600 core (e600 core reference manual, p. 1-1)

The e600 core also implements the AltiVec instruction set architectural extension. The e600 core can dispatch and complete three instructions simultaneously. It incorporates the following execution units:
• 64-bit floating-point unit (FPU)
• Branch processing unit (BPU)
• Load/store unit (LSU)
• Four integer units (IUs):
— Three shorter latency IUs (IU1a–IU1c)—execute all integer instructions except multiply, divide, and move to/from special-purpose register (SPR) instructions.
— Longer latency IU (IU2)—executes miscellaneous instructions including condition register
(CR) logical operations, integer multiplication and division instructions, and move to/from
SPR instructions.
• Four vector units that support AltiVec instructions:
— Vector permute unit (VPU)
— Vector integer unit 1 (VIU1)—performs shorter latency integer calculations
— Vector integer unit 2 (VIU2)—performs longer latency integer calculations
— Vector floating-point unit (VFPU)

Last edited by pavlor on 06-Jun-2015 at 08:42 PM.

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scabit 
Re: PowerPC notebook - Status update
Posted on 6-Jun-2015 21:58:40
#49 ]
Super Member
Joined: 8-Jan-2005
Posts: 1667
From: Satellite Beach, FL USA

@cdimauro

Quote:
Sure: iBook and PowerBook


Oh...this thread is about a new current day development powerpc laptop. I thought you meant there was something else out there powerPc based being produced today.
I would have no problem if Hyperion were to port AmigaOs4 to a MAC laptop....but how old are these things? When were the last ones produced, and how do you get any sort of repair/servicing on them if something goes wrong?
I really like the idea of a new PowerPc laptop which would be produced today with slightly higher specs and could also run Amiga OS4...and Morph OS too!

Scott

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cdimauro 
Re: PowerPC notebook - Status update
Posted on 7-Jun-2015 8:01:45
#50 ]
Elite Member
Joined: 29-Oct-2012
Posts: 2794
From: Germany

@scabit

Quote:

scabit wrote:
@cdimauro

Quote:
Sure: iBook and PowerBook


Oh...this thread is about a new current day development powerpc laptop. I thought you meant there was something else out there powerPc based being produced today.

No. Sorry for the misunderstanding, but I only said that PowerPC laptops already existed. So, no new development.
Quote:
I would have no problem if Hyperion were to port AmigaOs4 to a MAC laptop....but how old are these things?

10 years or more.
Quote:
When were the last ones produced, and how do you get any sort of repair/servicing on them if something goes wrong?

They don't have formal repair services, but maybe some privates offer it, like there are privates which offers the same repair service for Amigas, Commodore 64s, etc..
Quote:
I really like the idea of a new PowerPc laptop which would be produced today with slightly higher specs and could also run Amiga OS4...and Morph OS too!

Scott

That's very unlikely, unfortunately. Developing a laptop costs more than developing an ATX/ITX/etc. motherboard.

Apple's laptops are cheap and offer comparable performance of currently available PowerPC SoCs. There are also CPU replacements for them, with the latest G4 available from Freescale (with 1MB of L2 cache, and some other changes, plus a much greater overclocking possibility).

I think that Hyperion should seriously take them in consideration, like the MorphOS team did.

Cesare

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cdimauro 
Re: PowerPC notebook - Status update
Posted on 7-Jun-2015 8:09:17
#51 ]
Elite Member
Joined: 29-Oct-2012
Posts: 2794
From: Germany

@pavlor: it's better to use the same SPEC benchmark. However, it remains a synthetic benchmark which very unlikely tests the Altivec unit, for example.

As I said, it's better to see benchmarks with real applications.

Aside this, you reported the e600 core specs, which isn't the same core used by G4s: it's derived from it, but it's different.

MPC7447A RISC Microprocessor Hardware Specifications:

This section summarizes features of the MPC7447A implementation of the PowerPC architecture.
Major features of the MPC7447A are as follows:
• High-performance, superscalar microprocessor
— Up to four instructions can be fetched from the instruction cache at a time.
— Up to 12 instructions can be in the instruction queue (IQ).
— Up to 16 instructions can be at some stage of execution simultaneously.
— Single-cycle execution for most instructions
— One instruction per clock cycle throughput for most instructions
— Seven-stage pipeline control
• Eleven independent execution units and three register files
— Branch processing unit (BPU) features static and dynamic branch prediction
– 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache
of branch instructions that have been encountered in branch/loop code sequences. If a target
instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can
be made available from the instruction cache. Typically, a fetch that hits the BTIC provides
the first four instructions in the target stream.
– 2048-entry branch history table (BHT) with 2 bits per entry for four levels of
prediction—not taken, strongly not taken, taken, and strongly taken
– Up to three outstanding speculative branches
– Branch instructions that do not update the count register (CTR) or link register (LR) are
often removed from the instruction stream.
– Eight-entry link register stack to predict the target address of Branch Conditional to Link
Register (bclr) instructions
— Four integer units (IUs) that share 32 GPRs for integer operands
– Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
multiply, divide, and move to/from special-purpose register instructions.
– IU2 executes miscellaneous instructions including the CR logical operations, integer
multiplication and division instructions, and move to/from special-purpose register
instructions.
— Five-stage FPU and a 32-entry FPR file
– Fully IEEE 754-1985–compliant FPU for both single- and double-precision operations
– Supports non-IEEE mode for time-critical operations
– Hardware support for denormalized numbers
– Thirty-two 64-bit FPRs for single- or double-precision operands
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
4 Freescale Semiconductor
Features
— Four vector units and 32-entry vector register file (VRs)
– Vector permute unit (VPU)
– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as
vector add instructions (for example, vaddsbs, vaddshs, and vaddsws).
– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as
vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and
vmladduhm).
– Vector floating-point unit (VFPU)
— Three-stage load/store unit (LSU)
– Supports integer, floating-point, and vector instruction load/store traffic
– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream
operations
– 3-cycle GPR and AltiVec load latency (byte, half word, word, vector) with 1-cycle
throughput
– 4-cycle FPR load latency (single, double) with 1-cycle throughput
– No additional delay for misaligned access within double-word boundary
– Dedicated adder calculates effective addresses (EAs)
– Supports store gathering
– Performs alignment, normalization, and precision conversion for floating-point data
– Executes cache control and TLB instructions
– Performs alignment, zero padding, and sign extension for integer data
– Supports hits under misses (multiple outstanding misses)
– Supports both big- and little-endian modes, including misaligned little-endian accesses
• Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,
respectively, in a cycle. Instruction dispatch requires the following:
— Instructions can only be dispatched from the three lowest IQ entries—IQ0, IQ1, and IQ2.
— A maximum of three instructions can be dispatched to the issue queues per clock cycle.
— Space must be available in the CQ for an instruction to dispatch. (This includes instructions that
are assigned a space in the CQ but not in an issue queue.)
• Rename buffers
— 16 GPR rename buffers
— 16 FPR rename buffers
— 16 VR rename buffers
• Dispatch unit
— Decode/dispatch stage fully decodes each instruction
• Completion unit
— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
instructions ahead of it have been completed, the instruction has finished execution, and no
exceptions are pending.
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor 5
Features
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
— Tracks unresolved branches and flushes instructions after a mispredicted branch
— Retires as many as three instructions per clock cycle
• Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set-associative instruction and data caches
— Pseudo least-recently-used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock cycle; data cache can provide four
words per clock cycle
— Caches can be disabled in software.
— Caches can be locked in software.
— MESI data cache coherency maintained in hardware
— Separate copy of data cache tags for efficient snooping
— Parity support on cache and tags
— No snooping of instruction cache except for icbi instruction
— Data cache supports AltiVec LRU and transient instructions
— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word
forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
• Level 2 (L2) cache interface
— On-chip, 512-Kbyte, eight-way set-associative unified instruction and data cache
— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
— A total 9-cycle load latency for an L1 data cache miss that hits in L2
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte, two-sectored line size
— Parity support on cache
• Separate memory management units (MMUs) for instructions and data
— 52-bit virtual address, 32- or 36-bit physical address
— Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments
— Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and
memory coherency enforced/memory coherency not enforced on a page or block basis
— Separate IBATs and DBATs (eight each) also defined as SPRs
— Separate instruction and data translation lookaside buffers (TLBs)
– Both TLBs are 128-entry, two-way set-associative, and use an LRU replacement algorithm.
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
6 Freescale Semiconductor
Features
– TLBs are hardware- or software-reloadable (that is, a page table search is performed in
hardware or by system software on a TLB miss).
• Efficient data flow
— Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256 bits.
— The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs.
— The L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache.
— As many as eight outstanding out-of-order cache misses are allowed between the L1 data cache
and the L2 bus.
— As many as 16 out-of-order transactions can be present on the MPX bus.
— Store merging for multiple store misses to the same line. Only coherency action taken
(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed).
— Three-entry finished store queue and five-entry completed store queue between the LSU and
the L1 data cache
— Separate additional queues for efficient buffering of outbound data (such as castouts and
write-through stores) from the L1 data cache and L2 cache
• Multiprocessing support features include the following:
— Hardware-enforced, MESI cache coherency protocols for data cache
— Load/store with reservation instruction pair for atomic memory references, semaphores, and
other multiprocessor operations

But it's more interesting the "Comparison with the MPC7447, MPC7445, and MPC7441" section (pagg.7-9), which reports several tables describing the microarchitectures' capabilities.

You can see that a G4 is a very respecatable chip, compared to the current PowerPCs offering.

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pavlor 
Re: PowerPC notebook - Status update
Posted on 7-Jun-2015 9:19:51
#52 ]
Elite Member
Joined: 10-Jul-2005
Posts: 9373
From: Unknown

@cdimauro

Quote:
it's derived from it, but it's different.


Different in what? Bigger cache?

Quote:
You can see that a G4 is a very respecatable chip, compared to the current PowerPCs offering.


Quote:
it's better to use the same SPEC benchmark. However, it remains a synthetic benchmark which very unlikely tests the Altivec unit, for example.


Both G4 and e6500 have similar AltiVec units. I don΄t think G4 would score any better. On the other hand, G4 is bottlenecked by slow memory interface (eg. G4 1666 MHz is faster in raw performance than PA6T and has much more powerful AltiVec, still it loses in video playback benchmarks).

Quote:
As I said, it's better to see benchmarks with real applications.


Without doubt.

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Hypex 
Re: PowerPC notebook - Status update
Posted on 7-Jun-2015 17:07:40
#53 ]
Elite Member
Joined: 6-May-2007
Posts: 10718
From: Greensborough, Australia

@cdimauro

For the past 10-15 years producing a PowerPC machine has been seemingly hard and at first there was similar if not equal power at an expense to now where there is lesser power and still an expense, compared to cheaper boards. On top of sourcing the chips.

But if this laptop can be produced with four cores at 64-bit it certainly is up there in the power stakes. And likely to be as expensive as a 17" PowerBook ever was.

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Hypex 
Re: PowerPC notebook - Status update
Posted on 7-Jun-2015 17:19:07
#54 ]
Elite Member
Joined: 6-May-2007
Posts: 10718
From: Greensborough, Australia

@scabit

The last ones were made in about 2005. So ten years old now and showing their age. So they don't have features like SATA and only have IDE. I don't know if any SATA-to-IDE adaptors work opr even fit inside a case. As to repairs, well it's pretty much eBay for spare parts or a spare and look up a fixing guide.

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olegil 
Re: PowerPC notebook - Status update
Posted on 8-Jun-2015 11:57:28
#55 ]
Elite Member
Joined: 22-Aug-2003
Posts: 5888
From: Work

@cdimauro

e600/G4 is closer to a renaming than a derivation.

7448 uses e600, 7447 is G4.

However, buried in your TL;DR posts is an important point. e5500 and e6500 are beefed up e500 cores, not beefed up e600 cores. Comparing MIPS numbers across families is hard, so we're gonna need some real-world data on this one.

It's hard for a G4 with 133/166 or even 200MHz FSB to compete with triple DDR3 1866 also. Essentially, the T4 has 28 times higher bandwidth to memory than even the 7448.

Also, you're ONLY concerned with single-thread performance, the rest of us are still hopeful there's gonna be some SMP benefit here.

Edit: Now I found the 8641D datasheet, it lists exactly the same core features as the 7447 you quote, no surprises there.

Last edited by olegil on 08-Jun-2015 at 01:12 PM.

_________________
This weeks pet peeve:
Using "voltage" instead of "potential", which leads to inventing new words like "amperage" instead of "current" (I, measured in A) or possible "charge" (amperehours, Ah or Coulomb, C). Sometimes I don't even know what people mean.

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megol 
Re: PowerPC notebook - Status update
Posted on 8-Jun-2015 12:58:55
#56 ]
Regular Member
Joined: 17-Mar-2008
Posts: 355
From: Unknown

DMIPS = Dhrystone MIPS

Dhrystone was an improvement over (most) benchmarks in use when it was created. But it was and is not real world code, it is so small it fit into the L1 I-cache and it is very sensitive of compiler optimizations.

That means one can really only use it to compare similar processors running the _same_ compiler version using the same optimization settings. And even then it doesn't say much.

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olegil 
Re: PowerPC notebook - Status update
Posted on 8-Jun-2015 13:14:56
#57 ]
Elite Member
Joined: 22-Aug-2003
Posts: 5888
From: Work

@megol

On the other hand, there are a limited number of ways to compare REAL WORLD statistics without REAL boards IN OUR HAND. Comparing one game on one hardware to another game on another hardware also becomes pretty futile. But there's always lame/blender benchmarks, eh?

_________________
This weeks pet peeve:
Using "voltage" instead of "potential", which leads to inventing new words like "amperage" instead of "current" (I, measured in A) or possible "charge" (amperehours, Ah or Coulomb, C). Sometimes I don't even know what people mean.

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Hammer 
Re: PowerPC notebook - Status update
Posted on 8-Jun-2015 14:14:25
#58 ]
Elite Member
Joined: 9-Mar-2003
Posts: 4448
From: Australia

@cdimauro

Quote:

cdimauro wrote:
As you can see, the last models have the latest G4 processors, which had good performance (and Altivec too).

While it's good to see alternatives, what's special about Altivec when Intel AVXv2 (with FMA + 256bit SIMD) and Intel Iris Pro smashes Altivec solution?


Last edited by Hammer on 08-Jun-2015 at 02:18 PM.
Last edited by Hammer on 08-Jun-2015 at 02:15 PM.

_________________
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olegil 
Re: PowerPC notebook - Status update
Posted on 8-Jun-2015 14:23:02
#59 ]
Elite Member
Joined: 22-Aug-2003
Posts: 5888
From: Work

@Hammer

Oh not again.

_________________
This weeks pet peeve:
Using "voltage" instead of "potential", which leads to inventing new words like "amperage" instead of "current" (I, measured in A) or possible "charge" (amperehours, Ah or Coulomb, C). Sometimes I don't even know what people mean.

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KimmoK 
Re: PowerPC notebook - Status update
Posted on 9-Jun-2015 8:12:19
#60 ]
Elite Member
Joined: 14-Mar-2003
Posts: 5209
From: Ylikiiminki, Finland

Copypaste from wiki, it clears some things about e5500:
"The e5500 is based on the e500mc core and adds some new instructions introduced in the Power Architecture 2.06 specification, namely some byte- and bit-level acceleration; Parity, Population count, Bit permute and Compare byte. The FPU is taken straight from the PowerPC e600 core, which is a classic fully pipelined dual precision IEEE 754 unit running at full core speed and supports conversion between 64-bit floats and integers, effectively twice as fast as the FPU in e500mc. The e5500 also introduces an enhanced branch prediction unit with an 8-entry link stack.

The e5500 core is the first 64-bit Power Architecture core designed solely by Freescale and was introduced at Freescale Technology Forum in June 2010. Simulated models were available in July 2010, hard samples in late 2010 and full scale manufacturing the second half of 2011. Freescale have used the e700 and NG-64 monikers to refer to a very similarly speced core since 2004, but they are not the same product."

Also e6500 is summarized nicely:
"It has a revised memory subsystem compared to the previous e5500 core with four cores combined into a CPU Cluster, sharing a large L2 cache and the e6500 cores supports up to eight CPU Clusters for very large multiprocessing implementations. The core is the first multithreaded core designed by Freescale and reintroduces an enhanced version of AltiVec to their products. The multithreading allows for two virtual cores per hard core and is organized as 2x2-way superscalar.[1] One virtual core in an e6500 can often perform better than an entire e5500 core since Freescale essentially duplicated a lot of logic instead of just virtualizing it, in addition to other enhancements to the core.

Each core has five integer units (four simple and one complex), two load-store units, one 128-bit AltiVec unit, 32+32 kB instruction and data L1 caches. Speeds range up to 2.5 GHz, and the core is designed to be highly configurable via the CoreNet fabric and meet the specific needs of embedded applications with features like multi-core operation and interface for auxiliary application processing units (APU)."

Last edited by KimmoK on 09-Jun-2015 at 08:37 AM.
Last edited by KimmoK on 09-Jun-2015 at 08:35 AM.

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// For freedom, for honor, for AMIGA
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// Thing that I should find more time for: CC64 - 64bit Community Computer?

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