@OlafS25

Amen to that!

@OlafS25

Quote:

OlafS25 wrote: If the hardware is very very cheap some people might be tempted to buy it despite shortcomings. But no price or date yet. But of course we can continue for the next 10 months propably

Except for the amount of RAM it's quite likely that a Tabor hitting FPU-opcodes will be easily outperformed by an EFIKA, a prodct that did not sell like hot cakes for 99$ 8 years ago......

Last edited by Kronos on 01-Nov-2015 at 01:39 PM.

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@pavlor

Quote:

MPC8640D

So a board with PCI-e X8 isn't better than boards with PCI-e X4 (SAM460 )?

The primary issue with the 8640/8641 is that it really needs a Southbridge.

Last edited by iggy on 01-Nov-2015 at 02:04 PM.

@Kronos

Quote:

a prodct that did not sell like hot cakes for 99$ 8 years ago

It would sell better with the right OS and name.


On the other hand, MorphOS community in my "low-income" country nearly doubled thanks to Efika.

@pavlor

I liked the price and the availability from Directron was great.
If they had ever doubled the memory (which is pretty straight forward), I would have snapped one up.

Tabor will never been priced that low.

@Kronos

Except for the A1222 has DDR3 memory bus (up to 8gb ram) and Gen 2 PCI Express. A totally modern platform compared to the old Efika.

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Why P10xx and other Freescale CPU types from that generation have this SPE unit? For what they are using it? Is this something like primitive and slow Altivec (very strong word)?

Is it technically possible to use SPE to archieve performance like some kind of coprocessor that can run other things while CPU is doing main tasks? Maybe someone with enough technical knowledge can answer that.....

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@amigakit

Quote:

Gen 2 PCI Express

Interesting, I didn´t find this one in documentation.

@dooz

Quote:

Why P10xx and other Freescale CPU types from that generation have this SPE unit?

Hard to say... maybe Freescale thought it will lower power requirements in comparison to regular FPU.

Quote:

For what they are using it?

FPU.

Quote:

Is this something like primitive and slow Altivec (very strong word)?

No (however, there is some connection form application´s point of view...).

@dooz

Quote:

Why P10xx and other Freescale CPU types from that generation have this SPE unit? For what they are using it? Is this something like primitive and slow Altivec (very strong word)?

https://en.wikipedia.org/wiki/Cell_(microprocessor)#Synergistic_Processing_Elements_.28SPE.29

it's not like AltiVec, AltiVec is just some extra opcodes.

SPE is different beast, it’s a complete coprocessor as you say, you upload a program to it, so program can only do one thing, this make SPE bad for desktop operating systems.

The SPE should be pretty fast, but considering that programs are not written to use SPE, it might be a lot of work to support.

SPE has SIMD support (Singe Instruction Multiple Data.)
(AltiVec is a SIMD instruction set.)

Last edited by NutsAboutAmiga on 01-Nov-2015 at 02:40 PM.
Last edited by NutsAboutAmiga on 01-Nov-2015 at 02:38 PM.

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@amigakit

Quote:

amigakit wrote: @Kronos Except for the A1222 has 3 winged pink unicorns wearing wonderbras

You do understand that "a Tabor hitting FPU-opcodes" will degenerated it's performance by anywhere x10 to x100 (depending on the mix of FPU and non-FPU opcodes) ?

Noone ever claimed that Tabor will be slower as an EFIKA while running native code, but running "normal" PPC code it will suffer for sure.

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@NutsAboutAmiga

Quote:

The SPE should be pretty fast

Actually, in comparisons, it isn't.
Which is why Freescale went back to a conventional fpu when the e500mc core was introduced.

But if native code is compiled for the P1022, the hit will not be anywhere near what trapping and conversion will cost.

@iggy

Quote:

So a board with PCI-e X8 isn't better than boards with PCI-e X4 (SAM460 )?

Doesn't really matter since system will be CPU bound way before PCI-e bandwidth to GFX card is problem.

@iggy

Quote:

But if native code is compiled for the P1022, the hit will not be anywhere near what trapping and conversion will cost.

No in that case you write for example a new H264 decoder you upload to SPE. The SPE has local memory that is only fast if you DMA chunks of memory to it, but memory in SPE is limited in size.

I'm sure the SPE is fun to play with, but I don't think it's easy to use, this is complicated and I don't see how you can use SPE, to emulate a normal FPU.

What I do if where to emulate doubles using floats is truncate the number, I'm not sure how you do that precisely.

Last edited by NutsAboutAmiga on 01-Nov-2015 at 05:19 PM.
Last edited by NutsAboutAmiga on 01-Nov-2015 at 05:18 PM.
Last edited by NutsAboutAmiga on 01-Nov-2015 at 05:15 PM.
Last edited by NutsAboutAmiga on 01-Nov-2015 at 05:13 PM.

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@NutsAboutAmiga

I found some document from Freescale about use of SPE. The tite is "Improving DSP Performance Using Efficient SPE Coding".

http://cache.freescale.com/files/microcontrollers/doc/app_note/AN3733.pdf

The description is about "vector part" of SPE. "FPU part" is not described. It is really for MPC5500 family (e200 core). But it might be that this is the similar SPE that is in e500v2 core.

It is exact concept like you described.

These are some facts from the document:

The signal processing engine (SPE) on the MPC5500 family of devices allows multiple data operations to be performed by a single instruction. This feature is aimed at DSP operations, where the use of the SPE will increase system performance.

The SPE APU is not a coprocessor, and therefore doe s not perform SPE instructions in parallel to the e200z3/6 core. It uses the sa me pipeline and is subject to the same re strictions in bandwid th as the standard Book E instruction set. The advantage that the SPE offe rs is that it can perfor m multiple data operations for a single instruction, wherea s Book E is limited to one da ta operation per instruction.

So except "FPU part" we have some kind of DSP support inside P1022 that programmers can use

@pavlor

Quote:

pavlor wrote: @cdimauro Quote: "Like playing two different 3D games at the same time, for example. Or one 3D game which splits the display processing to the two cards, albeit using only one to display the final framebuffer." This is certainly not possible.

So the graphic cards can only display the content of the respective framebuffers. Not so much...


@dooz

Quote:

dooz wrote: Why P10xx and other Freescale CPU types from that generation have this SPE unit? For what they are using it?

It's an economic solution for the embedded market.
Quote:

Is this something like primitive and slow Altivec (very strong word)?

It's not like Altivec. Altivec is much more versatile and powerful.

The SPE unit offer something like "DSP extensions" that other processors provide to double the processing power with very low cost.
Quote:

Is it technically possible to use SPE to archieve performance like some kind of coprocessor that can run other things while CPU is doing main tasks?

No. It isn't a coprocessor, but a functional unit of the same core.


@NutsAboutAmiga

Quote:

NutsAboutAmiga wrote: @dooz Quote: Why P10xx and other Freescale CPU types from that generation have this SPE unit? For what they are using it? Is this something like primitive and slow Altivec (very strong word)? https://en.wikipedia.org/wiki/Cell_(microprocessor)#Synergistic_Processing_Elements_.28SPE.29 it's not like AltiVec, AltiVec is just some extra opcodes. SPE is different beast, it’s a complete coprocessor as you say, you upload a program to it, so program can only do one thing, this make SPE bad for desktop operating systems. The SPE should be pretty fast, but considering that programs are not written to use SPE, it might be a lot of work to support. SPE has SIMD support (Singe Instruction Multiple Data.) (AltiVec is a SIMD instruction set.)

e500v2's SPE unit has absolutely nothing to do with the SPE units integrated on the Cell processor.

Quote:

NutsAboutAmiga wrote: @iggy Quote: But if native code is compiled for the P1022, the hit will not be anywhere near what trapping and conversion will cost. No in that case you write for example a new H264 decoder you upload to SPE. The SPE has local memory that is only fast if you DMA chunks of memory to it, but memory in SPE is limited in size. I'm sure the SPE is fun to play with, but I don't think it's easy to use, this is complicated and I don't see how you can use SPE, to emulate a normal FPU. What I do if where to emulate doubles using floats is truncate the number, I'm not sure how you do that precisely.

Same as above: e500v2's SPE unit has NO local memory.


@dooz

Quote:

dooz wrote: @NutsAboutAmiga I found some document from Freescale about use of SPE. The tite is "Improving DSP Performance Using Efficient SPE Coding". http://cache.freescale.com/files/microcontrollers/doc/app_note/AN3733.pdf The description is about "vector part" of SPE. "FPU part" is not described. It is really for MPC5500 family (e200 core). But it might be that this is the similar SPE that is in e500v2 core. It is exact concept like you described. These are some facts from the document: The signal processing engine (SPE) on the MPC5500 family of devices allows multiple data operations to be performed by a single instruction. This feature is aimed at DSP operations, where the use of the SPE will increase system performance. The SPE APU is not a coprocessor, and therefore doe s not perform SPE instructions in parallel to the e200z3/6 core. It uses the sa me pipeline and is subject to the same re strictions in bandwid th as the standard Book E instruction set. The advantage that the SPE offe rs is that it can perfor m multiple data operations for a single instruction, wherea s Book E is limited to one da ta operation per instruction. So except "FPU part" we have some kind of DSP support inside P1022 that programmers can use

Do you really think that many coders will use it?

@cdimauro

Quote:

So the graphic cards can only display the content of the respective framebuffers. Not so much...

Yes. You can have one display connected to one card and one to another - like on classic Amiga. There were even more interesting combinations before introduction of Warp3D for Radeon SI: Radeon HD card for fast WB and most applications and Radeon 9250 for 3D games. In theory, it is possible to use 3 GFX cards on X1000 (2 Radeon HD(s) in PCIe slots and 1 Radeon 9250 in PCI or PCIe slot via PCIe2PCI adapter), but I don´t know anyone with such working setup.

Last edited by pavlor on 01-Nov-2015 at 06:39 PM.

@pavlor

Quote:

You can have one display connected to one card and one to another - like on classic Amiga.

Funny you had to point that out.
It is the primary reason I have two cards in my PC.

So that each display gets the full rendering power of an entire GPU.

Well, this might be a stupid question.....

We have two e500v2 cores in P1022. So do we have one SPE unit per core or only one SPE in P1022?

I cant see SPE unit in block diagrams of P1022.

Last edited by dooz on 03-Nov-2015 at 09:06 PM.

@dooz

That's wrong document as well, wrong core, your link is to 5500 core, not the 500 core.

Try this PDF.

http://cache.freescale.com/files/32bit/doc/app_note/AN3531.pdf

The signal processing engine (SPE), implemented on the e500v1 and e500v2, defines an alternative floating-point instruction set that uses GPRs rather than FPRs. See Section 3.1.2.1, “SPE Embedded Vector and Scalar Floating-Point Categories.”

In normal programs compiled with GCC, FPR's are used when passing arguments, in functions where floats / doubles are used.

Last edited by NutsAboutAmiga on 03-Nov-2015 at 09:57 PM.
Last edited by NutsAboutAmiga on 03-Nov-2015 at 09:55 PM.

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