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Gunnar 
Re: Packed Versus Planar: FIGHT
Posted on 12-Oct-2022 14:17:02
#601 ]
Regular Member
Joined: 25-Sep-2022
Posts: 152
From: Unknown

@FairBoy

Quote:

FairBoy wrote:
Since it got digged in all the feces you're smearing at each other:

I wanted to run "bustest" on my AmigaOne to verify those numbers mentioned earlier here but I only found the 68k version. Can somebody please point me to the PPC build of "bustest" because I don't want to measure the performance of the emulation layer, after all I want fair and correct results.


Hello Fairboy,

how are you?

Yes the traditional Bustest is 68k as many Amiga programs.

On PowerPC You can use the following test to measure this (MorphOS):
http://apollo-core.com/downloads/stream_mos

You can also use (PPC Linux)
http://apollo-core.com/minibench/minibenchv609_ppc32.exe

And you can compile and run this test
https://www.cs.virginia.edu/stream/

All of them will score comparable values.

I hope this helps you!

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Karlos 
Re: Packed Versus Planar: FIGHT
Posted on 12-Oct-2022 14:24:27
#602 ]
Elite Member
Joined: 24-Aug-2003
Posts: 3372
From: As-sassin-aaate! As-sassin-aaate! Ooh! We forgot the ammunition!

@Gunnar

Right. Essentially what you are saying is the system can only be as fast as the slowest rated component used in it. I suppose it's not possible, or perhaps not practical to have buffering logic like latches and stuff, between parts that might operate at different frequencies (before you roast me here, I'm a software engineer)...

In summary then, TINA could be fit with the retronym "Technically Impossible New Amiga".

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Gunnar 
Re: Packed Versus Planar: FIGHT
Posted on 12-Oct-2022 14:33:08
#603 ]
Regular Member
Joined: 25-Sep-2022
Posts: 152
From: Unknown

@Karlos

Quote:

Karlos wrote:
@Gunnar

Right. Essentially what you are saying is the system can only be as fast as the slowest rated component used in it.


This is kind obvious, no?


Quote:

In summary then, TINA could be fit with the retronym "Technically Impossible New Amiga".


What he promised was.
He will take the CPU from the Minimig.
We will take the same FPGA as the Mist.
This means his FPGA has the same speed.

But he promises to "magically" speed the CPU up to reach x40 faster speed.

40 times faster!
How difficult can this be for someone without FPGA experience?

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Karlos 
Re: Packed Versus Planar: FIGHT
Posted on 12-Oct-2022 14:35:57
#604 ]
Elite Member
Joined: 24-Aug-2003
Posts: 3372
From: As-sassin-aaate! As-sassin-aaate! Ooh! We forgot the ammunition!

@Gunnar

Quote:

Gunnar wrote:
@Karlos

Quote:

Karlos wrote:
@Gunnar

Right. Essentially what you are saying is the system can only be as fast as the slowest rated component used in it.


This is kind obvious, no?



Well, to you perhaps, but as a software engineer used to having to make things work that otherwise run at different speeds or completely asynchronously through various synchronisation mechanisms, not so much to me.

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Gunnar 
Re: Packed Versus Planar: FIGHT
Posted on 12-Oct-2022 15:22:39
#605 ]
Regular Member
Joined: 25-Sep-2022
Posts: 152
From: Unknown

@Karlos

Quote:

Quote:

[quote]
Right. Essentially what you are saying is the system can only be as fast as the slowest rated component used in it.


This is kind obvious, no?


Well, to you perhaps,
[/quote]

Hmm

Yes a system can never be faster than its slowest part.

This is the same everywhere, your car can not be faster than the engine provides, and the transmission support, and what the wheels support, and the tires.


But sorry we in last minute A37 preparations now ..
Lets continue to talk next week after the event.

And hey guys ... if you go to A37 .. come to us and say hello!

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kolla 
Re: Packed Versus Planar: FIGHT
Posted on 12-Oct-2022 17:22:27
#606 ]
Elite Member
Joined: 20-Aug-2003
Posts: 2377
From: Trondheim, Norway

@Gunnar

You are aware that “Minimig” as such has no CPU? Or rather, depending on what hardware the Minimig core is built for, one can chose between several options? If you mean TG68, then write TG68, don’t obfuscate things even further.

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B5D6A1D019D5D45BCC56F4782AC220D8B3E2A6CC

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kolla 
Re: Packed Versus Planar: FIGHT
Posted on 12-Oct-2022 18:26:35
#607 ]
Elite Member
Joined: 20-Aug-2003
Posts: 2377
From: Trondheim, Norway

@Gunnar

Quote:

Gunnar wrote:
Dear Friend Kolla


Quote:

And how about that open source SAGA


The suggested was that SAGA could be open sourced - when the SAGA development is fully finished.
So please be patient.


So never, then. It was all just a pointless exercise in an attempt to score "community points".

Open source is about working together _as a community_, not about “look how cool my stuff is… hey, why isn’t anyone interested?!”

Release early and release often.

Last edited by kolla on 12-Oct-2022 at 06:27 PM.

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Karlos 
Re: Packed Versus Planar: FIGHT
Posted on 12-Oct-2022 18:45:43
#608 ]
Elite Member
Joined: 24-Aug-2003
Posts: 3372
From: As-sassin-aaate! As-sassin-aaate! Ooh! We forgot the ammunition!

@kolla

Quote:
Release early and release often.


As we all get inexorably older, that's likely to take on a distinctly different and all together wetter meaning.

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cdimauro 
Re: Packed Versus Planar: FIGHT
Posted on 12-Oct-2022 21:00:30
#609 ]
Elite Member
Joined: 29-Oct-2012
Posts: 3097
From: Germany

@Gunnar

Quote:

Gunnar wrote:
Cesare Di Mauro,

Please tell why do you call me a liar,
when all I did was quoting a post from you and your friends?


Question:
Did you and your friends create a website advertising a vapor Amiga product,
claiming technically totally impossible values? Yes or No?

Question:
Did you and your friends post hundreds of false facts about this vapor Amiga product,
in Amiga forums? Yes or No?

Already replied here: https://amigaworld.net/modules/newbb/viewtopic.php?mode=viewtopic&topic_id=44581&forum=15&start=580&viewmode=flat&order=0#856017
Quote:
Quote:

- Cdmauro (software developer)
What's not clear to you about SOFTWARE word?


Cesare Di Mauro,

I hear that you said you only have software knowledge,

Wrong. Quote me and PROVE the contrary.
Quote:
therefore people can not expect that the "hardware facts" that you talk about are technically correct?

What about the hardware facts that you continue to post here every day?
Shall we also not expect them to be correct?

Clearly not, because they are coming from my knowledge about the programming the Amiga hardware.

Which has NOTHING to do with the knowledge about FPGA, RTL, HDL, etc., which is a completely different thing.
Quote:
Why do I talk about the TINA project?

No one can expect that every post a forum is correct.
Posts are often typed quickly, so misreading or mistyping is to be expected.



The TINA project was advertised for many month.
A lot of time was put into doing the website, a lot time was put into painting charts, into giving interviews, and into posting hundreds of "false TINA fact" in Amiga forums.

All KEY FACTS advertising the TINA project are wrong.

- Bus width is impossible
- memory speed is impossible
- clock rate is impossible

Please help me understand why did you ran around for month advertising a total vapor fake project?

Already replied here: https://amigaworld.net/modules/newbb/viewtopic.php?mode=viewtopic&topic_id=44581&forum=15&start=580&viewmode=flat&order=0#856017
Quote:

Gunnar wrote:
@Karlos

Hello Karlos,

Quote:

I agree that they shouldn't have been throwing around hypothetical figures like this until they knew the actual specification of the FPGA they intended to use, but just perhaps, they were looking at more than one option.


I see where you com from… I
You think they were not sure which FPGA to use?



This was not the case:
Cesare and his friends were very specific which FPGA they use.
And very clearly posted false facts for it.
Please take a look at the TINA website.


They posted they use three ALTERA CYCLONE 4, 30K C8
And they very clearly claimed an impossible clockrate of 470 Mhz.
You can see the 470MHz printed in each of the 3 FPGA in the picture.
And they claimed a totally impossible 128bit memory bus.

The whole thing is technical nonsense.
Their claimed internal 128bit bus is impossible too.


The false claimed clockrate of 470 MHz, is not a small mistake.
This is about 3 times more than what is technically possible with this FPGA family.


The false claimed 128bit memory bus is not a small mistake.
This is 4 times more than what this FPGA can do in reality.




Claiming 400% more than possible is not small mistake.
This is not like you brag "my car runs 130 miles/hour"
while in reality your car does only do "120 miles/hour".

This is like bragging "my car runs 480 miles per hour"
And you give interviews claiming this.
You making a website to claiming this.
And posting hundreds of forums repeating this false claim.!


Already replied here: https://amigaworld.net/modules/newbb/viewtopic.php?mode=viewtopic&topic_id=44581&forum=15&start=580&viewmode=flat&order=0#856017
Quote:

Gunnar wrote:
@Karlos

Quote:

I am in no position to disagree


You can also look at it the other way:
The FPGA is from the same company and has the same speed as the one used in the MIST.
The Minimig core is the CPU that he wanted to use.

This Minimig core reaches in the Mist ~40MHz.
He promised to reach ~ 470 MHz and to improve the core to not only do 1 instruction per cycle but 2 instead.

Who is "he"? The hardware engineer: bertocar. Go talk with him: I did nothing about the hardware (FPGA, HDL, etc.).
Quote:

Gunnar wrote:
@Karlos

Quote:

Karlos wrote:
@Gunnar

Right. Essentially what you are saying is the system can only be as fast as the slowest rated component used in it.


This is kind obvious, no?


Quote:

In summary then, TINA could be fit with the retronym "Technically Impossible New Amiga".


What he promised was.
He will take the CPU from the Minimig.
We will take the same FPGA as the Mist.
This means his FPGA has the same speed.

But he promises to "magically" speed the CPU up to reach x40 faster speed.

40 times faster!
How difficult can this be for someone without FPGA experience?

Again, he = bertocar, the hardware engineer. Certainly NOT me.

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MEGA_RJ_MICAL 
Re: Packed Versus Planar: FIGHT
Posted on 12-Oct-2022 23:33:23
#610 ]
Super Member
Joined: 13-Dec-2019
Posts: 1200
From: AMIGAWORLD.NET WAS ORIGINALLY FOUNDED BY DAVID DOYLE







⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀Ok, but what's better,
⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀packed - or planar?



⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀⠀/MEGA!







⠀⠀

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Hypex 
Re: Packed Versus Planar: FIGHT
Posted on 13-Oct-2022 2:41:03
#611 ]
Elite Member
Joined: 6-May-2007
Posts: 10883
From: Greensborough, Australia

@MEGA_RJ_MICAL

The answer is obvious: Packed-planar.

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Karlos 
Re: Packed Versus Planar: FIGHT
Posted on 13-Oct-2022 3:17:28
#612 ]
Elite Member
Joined: 24-Aug-2003
Posts: 3372
From: As-sassin-aaate! As-sassin-aaate! Ooh! We forgot the ammunition!

@Hypex

Plancked Pixels are best pixels.

Yes, I can't sleep.

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Hammer 
Re: Packed Versus Planar: FIGHT
Posted on 13-Oct-2022 3:43:24
#613 ]
Elite Member
Joined: 9-Mar-2003
Posts: 4611
From: Australia

@Gunnar

Quote:

Today all good FPU are fully pipelined.
Still all the FPU operation need several clock cycle to finish.


Zen 3 (family 19h) FPU instruction completion can vary from a latency of 1 to 19, and throughput instructions completion can range from 4 to 0.15 (XMM, DIVPD) or 0.07 (X87 FDIV).

FPU divides are usually slower while common FADD and FMUL instructions are fast instructions.

It depends on the instructions.

High clock speed is the brute force method for improving the slower instructions in relation to actual competition time. A high-clock speed target is part of the ASIC design.

Classic Pentium FPU has a feature that allows the slow FDIV to complete its calculation while letting through non-dependent FPU instructions to complete its pipeline execution. The classic Pentium FPU effectively has a limited out-of-order feature.


Quote:

Typically todays FPUs have about 6 or more operations in flight.
The 68080 can have up to 22 FPU operations in flight in parallel!

Instructions in the pipeline are in flight.

Modern X86 CPU's pipelines are many and the pipeline stages are deeper, but not crazy deep like the 31-stage Intel Prescott.

Zen 3 has six floating point pipelines and they are 256-bit wide.

The pipeline's depth has to be balanced with the upper clock speed target, latency, transistor budgets, and cost.


Quote:

And before you say INTEL has 16 register, no one needs more.
INTEL has more than 16 register. But INTEL "hides" them and uses them by implementing very costly hardware renaming logic.

When mass-produced with economies of scale, register renaming hardware is relatively cheap since Intel Celeron G6900 has the same Alder Lake Golden Cove P-core CPU as the high-end Core i9 12900K's Golden Cove P-cores.

For AMD, the lower-end SKU has the same CPU chiplet as the high-end CPU chiplet, the difference in yield quality, chiplet scaling, and AMD's asking price for good yields. AMD pays has the same price for bad, mediocre and good yields.

GpGPU takes many register count arguments to the extreme that smashed old-school RISC advocates' arguments.



Last edited by Hammer on 14-Oct-2022 at 03:11 AM.

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Bosanac 
Re: Packed Versus Planar: FIGHT
Posted on 13-Oct-2022 12:04:56
#614 ]
Regular Member
Joined: 10-May-2022
Posts: 234
From: Unknown

I'd like to make a complaint pleeeeeeeeeeeeeeeeease!
https://www.youtube.com/watch?v=ReJgCZ0DGnY

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bhabbott 
Re: Packed Versus Planar: FIGHT
Posted on 13-Oct-2022 18:58:20
#615 ]
Regular Member
Joined: 6-Jun-2018
Posts: 246
From: Aotearoa

@Hammer

Quote:

Hammer wrote:

When mass-produced with economies of scale, register renaming hardware is relatively cheap since Intel Celeron G6900 has the same Alder Lake Golden Cove P-core CPU as the high-end Core i9 12900K's Golden Cove P-cores.

More useless off-topic information.

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Hammer 
Re: Packed Versus Planar: FIGHT
Posted on 13-Oct-2022 21:48:44
#616 ]
Elite Member
Joined: 9-Mar-2003
Posts: 4611
From: Australia

@bhabbott

Quote:

bhabbott wrote:
@Hammer

Quote:

Hammer wrote:

When mass-produced with economies of scale, register renaming hardware is relatively cheap since Intel Celeron G6900 has the same Alder Lake Golden Cove P-core CPU as the high-end Core i9 12900K's Golden Cove P-cores.

More useless off-topic information.

Your argument is useless.

For context, READ
Quote:

And before you say INTEL has 16 register, no one needs more.
INTEL has more than 16 register. But INTEL "hides" them and uses them by implementing very costly hardware renaming logic.


The fuking Golden Cove Celeron is $59.00 AUD or $49.95 USD cheap, fool. https://pcpartpicker.com/products/cpu/#sort=price&page=1

Last edited by Hammer on 13-Oct-2022 at 09:52 PM.
Last edited by Hammer on 13-Oct-2022 at 09:49 PM.

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Bosanac 
Re: Packed Versus Planar: FIGHT
Posted on 13-Oct-2022 22:32:50
#617 ]
Regular Member
Joined: 10-May-2022
Posts: 234
From: Unknown

@Hammer

Quote:
But INTEL "hides" them and uses them by implementing very costly hardware renaming logic.



Quote:
The fuking Golden Cove Celeron is $59.00 AUD or $49.95 USD cheap, fool. https://pcpartpicker.com/products/cpu/#sort=price&page=1


I don't know whether to laugh or cry at this! :facepalm:

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Karlos 
Re: Packed Versus Planar: FIGHT
Posted on 13-Oct-2022 22:43:20
#618 ]
Elite Member
Joined: 24-Aug-2003
Posts: 3372
From: As-sassin-aaate! As-sassin-aaate! Ooh! We forgot the ammunition!

@Bosanac

I think we all need need a good long post with an over wide die shot or functional block diagram right about now.

Last edited by Karlos on 13-Oct-2022 at 10:45 PM.

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Hammer 
Re: Packed Versus Planar: FIGHT
Posted on 14-Oct-2022 3:30:25
#619 ]
Elite Member
Joined: 9-Mar-2003
Posts: 4611
From: Australia

@Bosanac

Quote:

Bosanac wrote:
@Hammer

Quote:
But INTEL "hides" them and uses them by implementing very costly hardware renaming logic.



Quote:
The fuking Golden Cove Celeron is $59.00 AUD or $49.95 USD cheap, fool. https://pcpartpicker.com/products/cpu/#sort=price&page=1


I don't know whether to laugh or cry at this! :facepalm:


It's amusing to see "But INTEL "hides" them and uses them by implementing a very costly hardware renaming logic" argument when Intel Celeron G6900 Alder Lake with two Golden Cove P-cores has a throw-away Raspberry Pi 3 Model B+ price range.


https://pcpartpicker.com/product/QKbTwP/intel-celeron-g6900-34-ghz-dual-core-processor-bx80715g6900
Intel Celeron G6900 Alder Lake (includes dual Golden Cove P-cores, UHD Graphics 710 iGPU) has a $59.00 AUD asking retail price.


https://core-electronics.com.au/raspberry-pi-3-model-b-plus.html?src=raspberrypi
Raspberry Pi 3 Model B+ has $58.10 AUD.


Last edited by Hammer on 14-Oct-2022 at 03:31 AM.

_________________
Ryzen 9 7900X, DDR5-6000 32 GB RAM, GeForce RTX 3080 Ti
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Hammer 
Re: Packed Versus Planar: FIGHT
Posted on 14-Oct-2022 3:43:28
#620 ]
Elite Member
Joined: 9-Mar-2003
Posts: 4611
From: Australia

@Gunnar

Quote:

Gunnar wrote:
@Karlos

Hello Karlos,

Quote:

I agree that they shouldn't have been throwing around hypothetical figures like this until they knew the actual specification of the FPGA they intended to use, but just perhaps, they were looking at more than one option.


I see where you com from… I
You think they were not sure which FPGA to use?



This was not the case:
Cesare and his friends were very specific which FPGA they use.
And very clearly posted false facts for it.
Please take a look at the TINA website.


They posted they use three ALTERA CYCLONE 4, 30K C8
And they very clearly claimed an impossible clockrate of 470 Mhz.
You can see the 470MHz printed in each of the 3 FPGA in the picture.
And they claimed a totally impossible 128bit memory bus.

The whole thing is technical nonsense.
Their claimed internal 128bit bus is impossible too.


The false claimed clockrate of 470 MHz, is not a small mistake.
This is about 3 times more than what is technically possible with this FPGA family.


The false claimed 128bit memory bus is not a small mistake.
This is 4 times more than what this FPGA can do in reality.




Claiming 400% more than possible is not small mistake.
This is not like you brag "my car runs 130 miles/hour"
while in reality your car does only do "120 miles/hour".

This is like bragging "my car runs 480 miles per hour"
And you give interviews claiming this.
You making a website to claiming this.
And posting hundreds of forums repeating this false claim.!



470 Mhz claim is based on the maximum PLL input for Cyclone IV.

http://www.altera.com/literature/hb/cyclone-iv/cyclone4-handbook.pdf
Look at Table 1–25. PLL Specifications for Cyclone IV Devices (p470)

Reading further, 433 MHz is too fast for a GPIO pin.

CPU design is different from the maximum PLL input.



It's a nothing burger i.e. does nothing for the classic Amiga 68K.

Yet another "Amiga Anywhere" type plan wouldn't impress the retro Amiga 68K users' majority.

Last edited by Hammer on 14-Oct-2022 at 03:47 AM.

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