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matthey 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 23-Jul-2024 19:15:09
#261 ]
Elite Member
Joined: 14-Mar-2007
Posts: 2462
From: Kansas

Hammer Quote:

The longer is relative. Longer when compared to (insert your CPU).


Longer compared to the higher end PPC604 with a double precision FPU.

https://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/ppcg3%20(mpr).pdf Quote:

The 604 core has an important advantage in its double precision floating-point multiplier. Arthur retains the single precision multiplier of the 603, which requires extra cycles for DP operations. As a result, the 604 core is 33% faster than Arthur’s core on SPECfp95, which makes heavy use of DP multiplication. Even taking Arthur’s L2 cache bus and 20% faster clock speed into account, the 604e appears to be a better solution for double-precision floating-point applications.


FPU instruction latency/throughput of instructions
Year | CPU | fadd.s | fadd.d | fmul.s | fmul.d | fdiv.s | fdiv.d

1993 Pentium 3/1 3/1 3/1-2 3/1-2 22/22 36/36
1993 PPC601 4/1 4/1 ? 4/2 ? 31/29
1994 68060 3/3 3/3 3/3 3/3 37/37 37/37
1994 PPC603 3/1 4/2 3/1 4/2 18/18 33/33
1994 PPC604 3/1 3/1 3/1 3/1 18/18 31/31

The PPC603 FPU compromise minimally affected timings but it significantly reduced the important double precision performance. Single precision fp is often adequate for 3D and DSP like workloads but C compilers defaulted to double precision or better. There was minimal support for single precision fp in C until C99 (~1999). Single precision in C was a kludge up until C99 and programmers rarely programmed PPC in assembly. This is in contrast to x86 and the 68k where it was not unusual for the CW and FPCR to be changed by assembly inlines or functions. The PPC603 targeted embedded use where high performance single precision fp was useful but the lack of assembly friendliness was a major handicap which was the opposite of the 68k, one of the most friendly CPUs to program in assembly ever. Embedded customers fled to ARM which was not as good as the 68k but much better than PPC and cheaper.

Hammer Quote:

68040 has a single instruction issue per cycle decoder.

68040 FPU is not fast.


The year has to be considered. The 68040 was released in 1990 and was over a year late. The FPU performance was reason

FPU instruction latency/throughput of instructions
Year | Chip | fadd.d | fmul.d | fdiv.d

1984 68881 51/51 71/71 103/103
1989 80486 8-20/8-20 14/14 73/73
1990 68040 7/3 9/5 42/38

The 68040 FPU has pretty good timings and is partially pipelined. Integer instructions can execute in parallel with a FPU instruction and a FMOVE instruction can sometimes be performed in parallel too. Multi-issue/dispatch is not as important for multi-cycle FPU instructions. Recall that the 68060 is better at multi-instruction dispatch than the Pentium but this does not make the 68060 FPU better. The 68040 had a more competitive desktop FPU than the later 68060 FPU which was a low latency minimalist embedded FPU.

Hammer Quote:

IBM PPC 602 @ 66Mhz's 1 million transistor budget is designed for 3DO M2.

IBM offered two low-priced PPC 602 @ 66Mhz for 3DO M2.

A game console designed around the expensive price of 68040? LOL.


I would rather have one 68040 (or PPC603 if forced to choose PPC) than two PPC602s. One PPC603 was chosen for the Apple Pippin but it died for many reasons including still poor performance from the PPC603. The Sega decision to use two SH-2 CPUs in the Saturn was also a poor idea. Two weak CPUs is not as good as one powerful CPU and a single powerful CPU is much easier to program. The 68060 is a better choice for a console in the mid to late 1990s. Negotiate a license and clock up that 8-stage pipeline. It's high integer performance, mediocre FPU performance, low power and reasonably low transistor count for the performance. The 1996 N64 NEC VR4300@93.75MHz CPU is shown as using 4.6 million transistors on several web sites.

https://www.nintendo64ever.com/Nintendo-64-Technical-Specifications.html

The MIPS CPU has 16kiB instruction and 8kiB data cache so developers were starting to figure out that RISC needs larger caches but they need to double the instruction cache again to reach the instruction cache performance of the 68060. The MIPS CPU uses a 5-stage scalar pipeline where the 68060 pipeline is 8-stage superscalar allowing it to use either cheaper silicon or clock it up more but it doesn't need to because it has better performance efficiency (performance/MHz). The 68060 32-bit design contributed to the transistor savings over the 64-bit CPU which Nintendo abandoned on their next console. The problem was that a 68060@50MHz was off the radar even though it had an 8-stage pipeline that should have allowed 150MHz and Motorola was pushing PPC instead. The 68060 has so much more potential than the PPC603(e) though.

Hammer Quote:

68060 has 4 byte fetch per cycle from the L1 instruction cache.

68060 has a 32-bit external bus when the competition has a 64-bit external bus.

Quake demo1 on 68060 @ 50 Mhz is 10 fps.


With just a 4 byte/cycle fetch and a 32-bit data bus, Quake should have been at 30fps on a 68060@150MHz. The upgraded 68060+ with 20%-30% more performance at the same frequency from doubling the caches is possible without more expensive silicon, more expensive memory or much development cost. Motorola was planning to leverage the cost advantage and efficiency of the 68060 to make high performance systems cheaper instead of targeting the diminishing returns of ultra high performance. Motorola needed this to improve the economies of scale for the 68k line but they abandoned the 68k for PPC instead.

Hammer Quote:

The major tax for fat 68K is Motorola's price.


The problem is not price but price efficiency (performance/$). The 68040 had good performance efficiency (performance/MHz) but was too hot to clock up for better performance without lowering the voltage which also required an expensive die shrink. The 68060 was designed for low power and with an 8-stage pipeline so it could be clocked up to increase the performance. All that is required to sabotage the performance is to hold the frequency down which is exactly what Motorola did to keep it from competing with clock limited shallow pipeline PPC designs. Motorola sacrificed the 68k, including the great 68060, to improve PPC economies of scale. The shallow pipeline PPC designs were not competitive and Jobs abandoned PPC. Motorola's big bet on PPC lost the desktop and workstation markets to Intel and the embedded market to ARM.

Last edited by matthey on 25-Jul-2024 at 06:27 AM.

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cdimauro 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 23-Jul-2024 20:46:05
#262 ]
Elite Member
Joined: 29-Oct-2012
Posts: 4127
From: Germany

@Hammer

Quote:

Hammer wrote:
@cdimauro

Quote:

You're comparing two completely different systems.

A fair comparison would have had only the CPU changed, while keeping everything else the same. Which is clearly not possible.

They run a similar Tomb Raider game. There are many common PlayStation and PC game ports.

Ken Kutaragi's 1 million transistor budget is about delivering the PlayStation product within a certain budget.

The CPU is only a single aspect of the total system cost.

That's exactly why there cannot be comparisons like those, because PS and PCs have very different hardware.

The only thing that you could do is testing software-only applications/games, but still you're factoring in also the chipset & memory used (e.g.: it's not possible to test only the CPUs).
Quote:
A1200/CD32 has certain BOM cost targets which is similar to game consoles.

Most consoles were much cheaper. A1200 and CD32 could be compared to the most expensive ones.
Quote:
Good luck with designing a $599 retail-priced A1200-like games bias machine from 486DX4.

You don't. You needn't. You've to recall what the primary market for the Amiga was.
Quote:
The main reason for Amiga Hombre is CSG's lower production cost compared to buying a CPU solution which includes 3rd party CPU's profit margins.

Dr Hepler selected the PA-RISC instruction set.

Which unfortunately was crap, since it required TONS of caches to get proper performance.
Quote:
Lew Eggebrecht favored the MIPS and PowerPC instruction set.

Nothing extraordinary compared to the equivalent 68k.

However, it's not clear about which period of time you are taking about. It makes sense (and actually that was about all undergoing discussions) to go up to 1992, when the AGA machines were released, and then 1993 for CD32. After that period there's the AAA drama and the Commodore bankrupt, so it doesn't make any sense to go beyond that.

What makes sense it taking a look at the period after that the Amiga 1000 was released, and check what was possible according to the technology of the time AND the primary market for the platform. Anything else isn't interesting.
Quote:
For Sony, LSi is willing to customize R3000A for Sony's target price.

See above: > 1993.
Quote:
In modern times, AMD customized Sony's Zen 2 design with the entire AVX pipeline being deleted for cost reduction.

Same here.
Quote:

From Commodore The Final Years by Brian Bagnall

Quote:
Commodore’s Ted Lenthe began looking into RISC chips with the AAA chipset back in the summer of 1989, specifically the Motorola 88000. But the engineers always balked at concrete plans due to the incompatibility problems a new processor would cause. For his part, Ed Hepler favored creating his own RISC CPU on the basis that Commodore could produce it much cheaper than buying the 88000 from Motorola.

And what was the outcome? Where is this custom RISC?
Quote:
Intel X86 has license complexity issues i.e. Intel vs AMD court battles.

Pat Gelsinger's Intel is willing to customize CPU cores for game console platform customers (1,2).

Reference
1. https://www.theregister.com/2022/02/14/intel_x86_licensing/
2. https://www.tweaktown.com/news/95974/intel-wants-to-be-inside-microsofts-next-gen-xbox-console-would-built-in-the-usa/index.html

A leadership change from Intel with game focus Xbox direction. Healthy competition is good in the X86 world.

Yes. However, this is > 1993.
Quote:
Quote:

Well, that's due to Commodore engineers which focused on that instead of attacking Amiga's primary market.

PowerAmiga refers to Escom era Amiga Technologies GmBH and Phase 5.

References
1. http://www.bambi-amiga.co.uk/amigahistory/atinfo.html
2. http://www.bambi-amiga.co.uk/amigahistory/pamiga97.html

OK, now it's clear and it's the same: > 1993.
Quote:

Hammer wrote:
@cdimauro

Quote:
Packed/chunky, yes, and before the AAA.


ET4000W32i with 386DX-16 level CPU is a joke.

First of all, such CPU on that period or time was good enough for the games of the time. Even for playing Doom.

Second, and more important, Amiga had dedicated hardware which could have contributed having had a proper evolution, and this even for the low-cost market (more to come on next articles).

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Hammer 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 24-Jul-2024 3:32:59
#263 ]
Elite Member
Joined: 9-Mar-2003
Posts: 6179
From: Australia

@matthey

Quote:

Longer compared to the higher end PPC604 with a double precision FPU.

FPU instruction latency/throughput of instructions
Year | CPU | fadd.s | fadd.d | fmul.s | fmul.d | fdiv.s | fdiv.d
1993 Pentium 3/1 3/1 3/1-2 3/1-2 22/22 36/36
1993 PPC601 4/1 4/1 ? 4/2 ? 31/29
1994 68060 3/3 3/3 3/3 3/3 37/37 37/37
1994 PPC603 3/1 4/2 3/1 4/2 18/18 33/33
1994 PPC604 3/1 3/1 3/1 3/1 18/18 31/31

That's unsustainable 68060's "throughput of instructions" when you have a 4-byte fetch per cycle from the L1 instruction cache and 32-bit bus bottleneck.

The throughput of instructions is only good as its weakest link.

For Quake, Warp1260's 68060 @ 100 Mhz with RTG hasn't shown Pentium 100 level performance.

When the CPU is used as a 3D rendering device, memory bandwidth is important.

The 3MB memory group of game consoles (3DO, Saturn, PS1) has discrete systems and video memory pools.

Quote:

I would rather have one 68040 (or PPC603 if forced to choose PPC) than two PPC602s. One PPC603 was chosen for the Apple Pippin but it died for many reasons including still poor performance from the PPC603.

Apple Pippin was sold at $599 (1995) which is expensive for a game console. Apple Pippin used IBM's PowerPC 603.

When Steve Jobs returned to Apple in 1997, he stopped all Macintosh clone efforts, which shut down the Pippin concept.

Apple Pippin's TAOS graphics processor was not made for good 3D rendering performance
https://youtu.be/bkA5MtwgxPo?t=46
Apple Pippin's Racing Days with jerky frame rates which is a bad 3D gaming experience.

Games for consoles were supposed to be designed for specific hardware that delivers a good gaming experience for the gamer.

Sony's PS1 for the win.

https://www.youtube.com/watch?v=MqEguAGAwQc
Apple Pippin is okay for Mac's Super Marathon 3D-rendered game.

After the game hardware is being mass-produced, the next problem is attracting 3rd party games. This is why Sony and Nintendo have strong 1st party games to solve the chicken vs egg problem.

My selection for Pentium @ 166 over CyberStorm's 68060 @ 50Mhz is the delivered 3D gaming experience with Quake. I estimated 68060's @ 50 Mhz performance in early 1996.

Quote:

The Sega decision to use two SH-2 CPUs in the Saturn was also a poor idea. Two weak CPUs is not as good as one powerful CPU and a single powerful CPU is much easier to program.

SuperH-2 is a 68040 class CPU at a low-cost price.

SuperH-2 can do 32b x 32b = 64b in 2 to 4 cycles.
SuperH-2 can do 16b x 16b = 32b in 1 to 3 cycles.
SuperH-2 can do 32b x 32b + 64 = 64b in 2 to 4 cycles. SuperH-2 is FMA capable.

For 3D at 68030 price range, SuperH-2 @ 28Mhz will murder 68030 @ 50Mhz.

Saturn's 2nd SuperH-2 CPU@ 28Mhz is a quick fix to close the gap with PS1's GTE (geometry, 66 MIPS @ 58 Mhz).

Saturn's custom hardware is based on sprites that are manipulated (warped) into 3D textures. The geometry and game logic are done on the SuperH-2 CPUs.

Without 3D acceleration, the gaming PC's Pentium equivalent has to factor in PS1's LSI R3000A @ 33Mhz and GTE @ 58 Mhz math and GPU (e.g. texture mapper) rendering processing capability.

Quote:

The 68060 is a better choice for a console in the mid to late 1990s.

FALSE.

Sega was looking at the 68030's price range. https://segaretro.org/History_of_the_Sega_Saturn/Development

Quote:

Negotiate a license and clock up that 8-stage pipeline. It's high integer performance, mediocre FPU performance, low power and reasonably low transistor count for the performance.

Again, Sega was looking at the 68030's price range. https://segaretro.org/History_of_the_Sega_Saturn/Development

Quote:

The 1996 N64 NEC VR4300@93.75MHz CPU is shown as using 4.6 million transistors on several web sites.

PS1's 1 million transistors budget was devised around the 1992 time period.

N64's MIPS R4300i CPU contained about 1.7 million transistors.

Quote:

With just a 4 byte/cycle fetch and a 32-bit data bus, Quake should have been at 30fps on a 68060 @ 150MHz.

1. 68060 Rev 6 has subpar overclocking.
2. 68060 lacks the 64-bit bus for mid-1990s lower-clocked memory modules.

Prove 150 Mhz EDO RAM's existence from 1994 to 1996.

68060's April 1994 release is too late for PS1's Q4 1994 release. PS1 is operational with Namco's close-door demonstration of Ridge Racer in December 1993.

During 1993 and 1994, Sony was building game developer relations for year 1993 operational PS1.

You have a timeline issue with DRAM tech's availability e.g. PC100 SDRAM was around 1997-1998 time period.


Last edited by Hammer on 24-Jul-2024 at 04:29 AM.
Last edited by Hammer on 24-Jul-2024 at 03:49 AM.
Last edited by Hammer on 24-Jul-2024 at 03:44 AM.

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Hammer 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 24-Jul-2024 4:22:26
#264 ]
Elite Member
Joined: 9-Mar-2003
Posts: 6179
From: Australia

@cdimauro

Quote:

That's exactly why there cannot be comparisons like those, because PS and PCs have very different hardware.

The only thing that you could do is testing software-only applications/games, but still you're factoring in also the chipset & memory used (e.g.: it's not possible to test only the CPUs).

If you tally up PS1's available processing power (i.e. 33 mips CPU + 66 mips GTE + texture mapper), it's more than 486DX4-100Mhz, hence Pentium class PC is recommended hardware for PS1 game ports.

Certain compute power from programmable or fixed functions is required to deliver a level of texture-mapped 3D gaming experience.

The 486 is a single instruction issue per cycle, hence a bottleneck for the available integer ALU and FPU hardware.

There are AMD's 5x86 clones starting from 133 Mhz to 160 Mhz that are faster than i486DX4-100, but slower than comparable clocked Pentium e.g. AMD's Am5x86-P75 has 133 Mhz clock speed with "Pentium 75" rating. Am5x86-P75 has a 16KB unified cache and a $93 introduction price in November 1995.

Thanks to IBM's "second source" clause, X86 clones can cover market segments that are not covered by Intel, hence strengthening the X86 PC platform as a whole. You can't say the same for the 68K world when Motorola has a tighter grip on 68K licensing.

IBM played a role in building the X86 CPU market with valid insurance.

Quote:

Most consoles were much cheaper. A1200 and CD32 could be compared to the most expensive ones.

CD32's total BOM is about $90 per unit i.e. $9 million last loan equates to 100,000 CD32s (cite: Commodore The Final Years by Brian Bagnall).

Quote:

See above: > 1993.

PS1 is known to be operational in Dec 1993 with its 1st game i.e. Namco's close-door demonstration of Ridge Racer.

Sony's LSI CPU development started around 1992.

During CD32's development, Psygnosis' meeting with Mehdi Ali and the push for upgraded CD32 hardware with minimal cost increase gives hints about PS1.

Sony's PlayStation developer relation initiatives was active in 1992.

Last edited by Hammer on 24-Jul-2024 at 04:37 AM.

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cdimauro 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 24-Jul-2024 4:37:21
#265 ]
Elite Member
Joined: 29-Oct-2012
Posts: 4127
From: Germany

@Hammer

Quote:

Hammer wrote:
@cdimauro

Quote:

That's exactly why there cannot be comparisons like those, because PS and PCs have very different hardware.

The only thing that you could do is testing software-only applications/games, but still you're factoring in also the chipset & memory used (e.g.: it's not possible to test only the CPUs).

If you tally up PS1's available processing power (i.e. 33 mips CPU + 66 mips GTE + texture mapper), it's more than 486DX4-100Mhz, hence Pentium class PC is recommended hardware for PS1 game ports.

Certain compute power from programmable or fixed functions is required to deliver a level of texture-mapped 3D gaming experience.

The 486 is a single instruction issue per cycle, hence a bottleneck for the available integer ALU and FPU hardware.

There are AMD's 5x86 clones starting from 133 Mhz to 160 Mhz that are faster than i486DX4-100, but slower than comparable clocked Pentium e.g. AMD's Am5x86-P75 has 133 Mhz clock speed with "Pentium 75" rating. Am5x86-P75 has a 16KB unified cache and a $93 introduction price in November 1995.

Thanks to IBM's "second source" clause, X86 clones can cover market segments that are not covered by Intel, hence strengthening the X86 PC platform as a whole. You can't say the same for the 68K world when Motorola has a tighter grip on 68K licensing.

IBM played a role in building the X86 CPU market with valid insurance.

The problem remains the same: you're including other things and don't focus only on the CPU.

If you compare an 80486 with a whole PlayStation, it obviously can't keep it up.

This part of the discussion was about which CPU could have been suitable for the new consoles. CPUs, and nothing else (e.g.: the chipset). Hence, my replies.
Quote:
Quote:

Most consoles were much cheaper. A1200 and CD32 could be compared to the most expensive ones.

CD32's total BOM is about $90 per unit i.e. $9 million last loan equates to 100,000 CD32s (cite: Commodore The Final Years by Brian Bagnall).

Which is good to know because it was largely profitable.

However, the discussion here was about the final prices to the customers, and not the BOM (BTW, we don't know it for the consoles. So, it's not possible to make comparisons even from this PoV).
Quote:
Quote:

See above: > 1993.

PS1 is known to be operational in Dec 1993 with its 1st game.

Sony's LSI CPU development started around 1992.

We're talking about the delivery time here: internal development is not relevant.

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Hammer 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 24-Jul-2024 4:49:53
#266 ]
Elite Member
Joined: 9-Mar-2003
Posts: 6179
From: Australia

@cdimauro

Quote:

cdimauro wrote:

The problem remains the same: you're including other things and don't focus only on the CPU.

If you compare an 80486 with a whole PlayStation, it obviously can't keep it up.

This part of the discussion was about which CPU could have been suitable for the new consoles. CPUs, and nothing else (e.g.: the chipset). Hence, my replies.

This topic is about the whole game console's processing chips.

CPU is only a single aspect of a game console.

I already covered the package costs for certain 486DX4 CPUs, the issue is Intel's profit policy i.e. need for a new CEO. Intel can enter the games console market with a changed profit policy. Pat's Intel will aim for Xbox Next and any large semi-custom customers.

Quote:

Which is good to know because it was largely profitable.

However, the discussion here was about the final prices to the customers, and not the BOM (BTW, we don't know it for the consoles. So, it's not possible to make comparisons even from this PoV).

There are estimated BOM cost breakdowns for game consoles.

Quote:

We're talking about the delivery time here: internal development is not relevant.

With PS1, there's extra time to build its game library. Again, PS1 was operational in Dec 1993 with its 1st game.

Sony didn't follow the "force launch" like CD32 and 3DO.

This topic has B2B cost debates. This is why I'm using Dataquest market intelligence and other wholesale pricing reports extensively.

BOM and B2B costs influence what's possible for retail.

Last edited by Hammer on 24-Jul-2024 at 05:04 AM.
Last edited by Hammer on 24-Jul-2024 at 04:59 AM.
Last edited by Hammer on 24-Jul-2024 at 04:56 AM.
Last edited by Hammer on 24-Jul-2024 at 04:54 AM.
Last edited by Hammer on 24-Jul-2024 at 04:51 AM.

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cdimauro 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 24-Jul-2024 5:08:03
#267 ]
Elite Member
Joined: 29-Oct-2012
Posts: 4127
From: Germany

@Hammer

Quote:

Hammer wrote:
@cdimauro

Quote:

cdimauro wrote:

The problem remains the same: you're including other things and don't focus only on the CPU.

If you compare an 80486 with a whole PlayStation, it obviously can't keep it up.

This part of the discussion was about which CPU could have been suitable for the new consoles. CPUs, and nothing else (e.g.: the chipset). Hence, my replies.

This topic is about the whole game console's processing chips.

CPU is only a single aspect of a game console.

I already covered the package costs for certain 486DX4 CPUs, the issue is Intel's profit policy i.e. need for a new CEO. Intel can enter the games console market with a changed profit policy.

It's the same. Yes, it was about new consoles, and it means: which CPU was suitable for them? Hence the (sub)discussion only focus on the CPU.
Quote:
Quote:

Which is good to know because it was largely profitable.

However, the discussion here was about the final prices to the customers, and not the BOM (BTW, we don't know it for the consoles. So, it's not possible to make comparisons even from this PoV).

There are estimated BOM cost breakdowns for game consoles.

Any data for them?
Quote:
Quote:

We're talking about the delivery time here: internal development is not relevant.

With PS1, there's extra time to build its game library. Again, PS1 was operational in Dec 1993 with its 1st game.

Sony didn't follow the "force launch" like CD32 and 3DO.

OK, but what matters is when a product arrives/d to the market.

Even the SNES was in development years before that, and engineers had to chose the proper elements (CPU, video chip, audio chip, ...).
Quote:
This topic has B2B cost debates. This is why I'm using Dataquest market intelligence and other wholesale pricing reports extensively.

BOM and B2B costs influence what's possible for retail.

I've no problem with those data: they are useful to understand what were the margins.

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bhabbott 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 24-Jul-2024 8:33:41
#268 ]
Cult Member
Joined: 6-Jun-2018
Posts: 509
From: Aotearoa

@Hammer

Quote:

Hammer wrote:

The Amiga had found its mass market as a good value gaming content creation and easy-to-use game player machine. Amiga's pixel art focus is game artwork content instead of publishing artwork content.

Gaming and creativity - most users weren't using Deluxe Paint to create game assets, they were painting with pixels.

Quote:
The Amiga doesn't need to copy Macintosh i.e. Commodore needs to focus on interactive entertainment business.

There is no shame in the entertainment business i.e. money is money.

I agree. Many Amiga fans don't though, and get upset when their precious Amiga is derided as being 'just a games machine' by snotty PC and Mac users.

Quote:
AAA moonshot project is a distraction from Amiga's "after-hours" mass market.

For a $1 billion company, Commodore is spreading itself too thin.

I agree 100%. But Commodore's engineers were infected with the same disease as Amiga fans - PC envy.

Quote:
Strong Commodore national subsidiaries like Commodore UK traded in the entirety of 1994.

Irrelevant. No Commodore International meant no future. Only hardcore Amiga fans with more love for the platform than business sense would continue developing for it (that didn't include me - our plans were instantly destroyed when Commodore died).

Quote:
In terms of population size and spending strength, you need to combine Germany and the UK to rival the Japanese market.

The Japanese market was irrelevant. Might as well be on a different planet.

Quote:
Doom wasn't a fad in 1998

Nope, it was of no commercial value anymore, hence why id released the source code. But this was 4 years later, and a lot had happened in those 4 years.

Quote:
A Tomb Raider port would be better since the PS1 baseline is fixed-point integer math and 68060 has pretty good fixed-point integer math performance.

Interesting. PC Tomb Raider needs the FPU. I will have to check the source code to see how the PlayStation does it.

Quote:
Wrong. Modern PC gaming's core experience is based on the current-generation game consoles' hardware.

I'm no expert on modern games, but this sounds wrong to me. You saying modern gaming PCs have console chips in them?

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matthey 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 24-Jul-2024 20:29:56
#269 ]
Elite Member
Joined: 14-Mar-2007
Posts: 2462
From: Kansas

Hammer Quote:

That's unsustainable 68060's "throughput of instructions" when you have a 4-byte fetch per cycle from the L1 instruction cache and 32-bit bus bottleneck.

The throughput of instructions is only good as its weakest link.


The 68060 FPU is not pipelined so the most common FPU instructions are sustainable.

1 cycle: FABS, FCMP, FMOVE, FNEG, FTST
3 cycle: FADD, FINT, FINTRZ, FMUL, FSUB
37 cycles: FDIV
68 cycles: FSQRT

The most common FPU instructions have a 3 cycle latency for FPU register arguments and are 4 bytes. The 68060 fetches 4 bytes per cycle which is 12 bytes per 3 cycles. The instruction buffer is usually filling when executing heavy fp code. FPU instructions with large immediates and displacements and/or integer code executing in parallel may actually drain the instruction buffer but, on average, the 4 bytes per cycle fetch is adequate. A 4 byte per cycle fetch would not be adequate to sustain a pipelined FPU where a FPU instruction is dispatched every cycle.

The 68060 FPU can fetch 8 bytes per cycle from the data cache which is much more common than from memory. This was a reasonable compromise with minimal performance loss used by many practical CPUs to reduce the CPU and memory cost for customers. Since we have been talking about consoles, the N64 MIPS CPU used a 64-bit CPU with a 32-bit data bus. There was a 1993 console with a x86 CPU in Japan called the FM Towns Marty which used a AM386SX that was 32-bit internally with a 16-bit data bus. The 68060 design was more practical for consoles and embedded use than the high end desktop/workstation Pentium design. The 68060 outperforms the Pentium in integer performance/MHz and is not far behind in compiled FPU performance/MHz while it should have been able to easily out clock it for a greater performance advantage.

Hammer Quote:

For Quake, Warp1260's 68060 @ 100 Mhz with RTG hasn't shown Pentium 100 level performance.

When the CPU is used as a 3D rendering device, memory bandwidth is important.


The largest impediment for 68060 performance is likely the lack of 68060 compiler support. The Pentium had huge compiler support but the stack based FPU ISA was difficult for compilers. Quake for the Pentium had man years of professional assembly optimizations too. The Pentium even had a major "software" advantage over the x86 competition because of Pentium specific optimizations.

Hammer Quote:

The 3MB memory group of game consoles (3DO, Saturn, PS1) has discrete systems and video memory pools.


Unified chipset memory instead of separate video and audio memory is nice. Unfortunately, there was not enough memory bandwidth at that time to unify CPU and chipset memory without VRAM which is why fast memory gave such a large performance boost.

Hammer Quote:

Apple Pippin was sold at $599 (1995) which is expensive for a game console. Apple Pippin used IBM's PowerPC 603.


One nice feature of the PPC603 is a selectable 32-bit or 64-bit data bus. The Pippin chose to use a 32-bit data bus with cheaper 32-bit memory (32 data lines in the pic).



The PPC603 8kiB instruction cache is like a 68060 2kiB instruction cache so the PPC603 has higher memory requirements to load code from memory that misses the too small instruction cache (loading code from memory can reduce data loaded from memory too). The designed for consoles PPC602 with only 4kiB instruction cache is like a 68060 1kiB instruction cache and would have been worse. It was soon discovered that even the PPC603 caches were inadequate and the PPC603e was emergency designed in less than a year, with double the caches and associative ways.

https://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/ppcg3%20(mpr).pdf Quote:

Larger Caches Aid Performance
A final performance boost comes from Arthur’s larger on-chip caches. The new chip includes 32K of instruction cache and 32K of data cache. This is twice the amount of cache found on the 603e and four times the cache size of the original 603. The 603’s tiny 8K caches were notoriously poor for Mac OS software, particularly for 68K emulation; even the 603e’s caches cause a significant performance hit at higher clock speeds. Given Arthur’s design target of 250 MHz and up, doubling the caches again made sense.


The 603e finally brought the instruction cache up to the performance level of a 68040 (half of a 68060) but it came at a cost.

CPU | pipeline | transistors | process size | data bus bits | surface mount pins
68060 8-stage 2,530,000 500nm 32 208
PPC603e 4-stage 2,600,000 330nm 32/64 240

The PPC603e received a die shrink too but is now using a more expensive process to increase the shallow pipeline clock speed and performance. The shallow pipeline was favored because it saves transistors in the pipeline and for branch prediction of which the PPC603e only has static prediction compared to the 68060 dynamic prediction. The shallow pipeline also minimizes load-to-use stalls common in RISC CPU designs with separate load/store units. Transistors from the caches already push the core size past the 68060 when using the same process which increases cost. The 32/64 bit selectable data bus is nice as it allows to select cheaper memory or higher performance memory but it still requires more CPU pins adding to the cost. Chip pins had cost something like $1 a piece in the 1980s but were obviously dropping quickly with the cost of transistors. In fact, the Microprocessor Report from February 1997 linked above gives a estimated manufacturing cost for the PPC603e of only $30, certainly based on huge mass production estimates. Moore's Law was kicking in hard but the 68060 was still very competitive at this time if it was brought up to speed and mass produced but it was designated to low clock speed embedded duty in Motorola's basement and ran under the radar by not clocking it up. Caches could not be doubled endlessly as the PPC604e with 32kIB I+D already had a lower clock speed than the PPC604 with 16kiB I+D which the PPC603e now had. The 68060 8kiB I+D could have been increased to 16kiB I+D at launch in 1994 and is almost certainly the major part of the 68060+ upgrade that was originally planned for the 68060. Arthur as mentioned in the article is the famous PPC G3 with caches increased to 32kiB I+D but this was made possible with another expensive die shrink to 250nm. The L2 cache was later introduced on a G3 CPU and this gave PPC a second wind as now instruction cache misses did not use as much memory bandwidth and large (L1) cache sizes did not limit the clock speed. On the other hand, caches were increasing much faster than pipeline logic which increased the advantage of code density. The code density advantage was enough to kill off "fat" classic RISC including Alpha, PA-RISC, MIPS, SPARC and PPC but the advantage is much larger today. Moore's Law has ended and SRAM for caches is scaling at a fraction of what it was while die shrinks are increasing in cost. Pipeline logic is continuing to scale which gives a further advantage to CISC designs.

Hammer Quote:

My selection for Pentium @ 166 over CyberStorm's 68060 @ 50Mhz is the delivered 3D gaming experience with Quake. I estimated 68060's @ 50 Mhz performance in early 1996.


Your Pentium@166MHz is at least a 3rd generation Pentium (P54CS or P55C) for the desktop and you are comparing to a 1st gen embedded 68060 CPU that Motorola sabotaged.

year | CPU | pipeline | transistors | process
1993 P5 5-stage 3,100,000 800nm
1994 P54C 5-stage 3,200,000 500nm
1995 P54CS 5-stage 3,300,000 350nm
1997 P55C 6-stage 4,500,000 350nm

1994 68060 8-stage 2,530,000 500nm

A 68060@150MHz should have been possible without an expensive die shrink and the transistor count was low enough to double the caches at introduction but Motorola decided to kill the Pentium killer because it was also a PPC killer.

Hammer Quote:

SuperH-2 is a 68040 class CPU at a low-cost price.

SuperH-2 can do 32b x 32b = 64b in 2 to 4 cycles.
SuperH-2 can do 16b x 16b = 32b in 1 to 3 cycles.
SuperH-2 can do 32b x 32b + 64 = 64b in 2 to 4 cycles. SuperH-2 is FMA capable.


SuperH has good code density but the 16-bit fixed length encoding is a handicap that greatly increases the number of instructions and memory traffic (code is removed from the predictable code stream and moved to less predictable data accesses). When ARM licensed SuperH, they changed their Thumb ISAs to a variable length 16/32 bit encoding which is a big improvement. SuperH is also RISC which is a handicap compared to the 68k when data is in cache/memory. SuperH is a descent low end embedded CPU but it doesn't scale up well. It does have DSP like extensions like FMA although I would not add it to a CISC integer ISA which is competitive without it when fully pipelined (SuperH added a FPU and fp FMA later which I do like for CISC). It is unfortunate that the 68060 removed 32b*32b=64b as it would otherwise be competitive with SH-2 FMA but 16b*16b+32b is competitive and likely outperforms SH-2 if any of the data is in cache/memory.

Hammer Quote:

For 3D at 68030 price range, SuperH-2 @ 28Mhz will murder 68030 @ 50Mhz.


The timings of the 68020/68030 instructions are underwhelming and the caches are small but once again you compare to a much later 1993 SH-2 with 4kiB unified cache. Motorola needed a 68k offering between the 68030 and 68040 with caches between since they were a major part of the 68040 cost. SH-2 was certainly a better value than the 68040 but the 68040 was nicer and had a FPU.

Hammer Quote:

Saturn's 2nd SuperH-2 CPU@ 28Mhz is a quick fix to close the gap with PS1's GTE (geometry, 66 MIPS @ 58 Mhz).

Saturn's custom hardware is based on sprites that are manipulated (warped) into 3D textures. The geometry and game logic are done on the SuperH-2 CPUs.

Without 3D acceleration, the gaming PC's Pentium equivalent has to factor in PS1's LSI R3000A @ 33Mhz and GTE @ 58 Mhz math and GPU (e.g. texture mapper) rendering processing capability.


The PS1 MIPS CPU was nothing special. If the PS1 3D was so good, Sony could have put it on a card and brought it to the desktop but there were better quality fp 3D cards available or on the way. They used a lot more power and were more expensive but these were not as important for desktop gaming.

Hammer Quote:

PS1's 1 million transistors budget was devised around the 1992 time period.

N64's MIPS R4300i CPU contained about 1.7 million transistors.


16kiB-I + 8kiB-D = 24kiB of caches

24kiB * 1024B/kiB = 24,576B * 8b/B = 196,608b * 6transistors/b = 1,179,648 transistors

If the MIPS CPU is only 1.7 million transistors, the 1,179,648 transistors of caches doesn't leave much room for 64-bit logic. The 4.6 million transistors some websites claimed seemed high though. Perhaps the claim is for the whole system (CPU+chipset)?

Hammer Quote:

1. 68060 Rev 6 has subpar overclocking.
2. 68060 lacks the 64-bit bus for mid-1990s lower-clocked memory modules.


The funny thing is that even without clocking it up and without a 64-bit data bus, the 68060 would have still made a better CPU for a console than a Pentium in the mid-1990s. The only thing missing was the economies of scale to make it cheap and that is what a console can do.

Let's take one more look at just how bad 50MHz is for an 8-stage pipeline CPU.

CPU@max clock rating ~500nm process | pipeline | MHz/stage
ARM710@40MHz 3-stage 13MHz/stage
PPC601+@120MHz 4-stage 30MHz/stage
PPC603@160MHz 4-stage 40MHz/stage
Pentium P54C@120MHz 5-stage 24MHz/stage
PPC604@180MHz 6-stage 30MHz/stage
HP PA-7300LC@180MHz 6-stage 30MHz/stage
HP PA-8000@180MHz 7-stage 26MHz/stage
Alpha 21064@300MHz 7-stage 43MHz/stage
MIPS R4400@200MHz 8-stage 25MHz/stage
68060@50MHz 8-stage 6MHz/stage
UltraSPARC@200MHz 9-stage 22MHz/stage

The average MHz/stage excluding the 68060 is 28MHz/stage while the 68060 is 6MHz/stage. A 68060@226MHz would have average MHz/stage. The best MHz/stage has 43MHz/stage which would give a 68060@344MHz. Excluding the 68060, the worst MHz/stage of 13MHz/stage would give a 68060@107MHz but that is based on a small and weak ARM embedded core. The case could be made that the Motorola/Freescale architects were incompetent but the Motorola PPC CPUs had better than average MHz/stage. No, it is obvious there was deliberate sabotage of anywhere close to normal design effort which likely involves identifying clock limiting logic and optimizing it and/or rebalancing the stages.

Hammer Quote:

Prove 150 Mhz EDO RAM's existence from 1994 to 1996.

68060's April 1994 release is too late for PS1's Q4 1994 release. PS1 is operational with Namco's close-door demonstration of Ridge Racer in December 1993.

During 1993 and 1994, Sony was building game developer relations for year 1993 operational PS1.

You have a timeline issue with DRAM tech's availability e.g. PC100 SDRAM was around 1997-1998 time period.


The 68060 did not have an integrated memory controller so it could be adapted for SDRAM but required external logic. Some memory controllers at the crossover supported many different types of memory. For example, the 1993 SH-2 integrated memory controller supported SDRAM, DRAM, PSRAM, Masked ROM and SRAM. It had 6 cycle 16B cache line fills from SDRAM. Hitachi did a good job with product pipelines and marketing for SuperH which is an area where Motorola/Freescale struggled. The 68k is a much better ISA than SuperH though.

Last edited by matthey on 24-Jul-2024 at 11:40 PM.
Last edited by matthey on 24-Jul-2024 at 11:34 PM.
Last edited by matthey on 24-Jul-2024 at 11:27 PM.
Last edited by matthey on 24-Jul-2024 at 08:44 PM.

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Hammer 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 25-Jul-2024 4:39:40
#270 ]
Elite Member
Joined: 9-Mar-2003
Posts: 6179
From: Australia

@matthey

https://www.yahoo.com/tech/nvidia-nearly-went-business-1996-151504041.html
Quote:

Nvidia nearly went out of business in 1996 trying to make Sega's Dreamcast GPU — instead, Sega America's CEO offered the company a $5 million lifeline.

(skip section)

And ultimately, Nvidia was still paid for its failed attempt at making the Dreamcast's GPU— thanks to then-CEO of Sega America, Shoichiro Irimajiri. When Huang came to Sega with the unfortunate news, he asked to still be paid in full for the contract, lest their company go out of business.

The answer picked by Irimajiri and Sega wound up being a $5 million investment into Nvidia, since Irimajiri had previously met Huang and taken a liking to him. While Irimajiri eventually stepped down from executive positions at Sega (and was briefly president of the whole company, not just the US branch), this investment was cashed out for $15 million afterward, helping keep Sega stable as the company departed the console business.


NVIDIA committed R&D resources for the Sega Dreamcast project.

From Sega's 5 million dollar lifeline investment, NVIDIA released RiVA 128 in 1997. NVIDIA has the employee skillset from SUN GX 3D workstations to quickly design RiVA 128 (NV3) for 1997 release after a disaster NV2 project.

For comparison:
Commodore UK managed to attract $50 million in investor money.

Commodore International's last lifeline loan is about $9 million for a batch of 100,000 CD32s.

Commodore International has a debt of over $110 million.

Last edited by Hammer on 25-Jul-2024 at 04:43 AM.

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Hammer 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 25-Jul-2024 6:05:13
#271 ]
Elite Member
Joined: 9-Mar-2003
Posts: 6179
From: Australia

@matthey

Quote:

The 68060 FPU is not pipelined so the most common FPU instructions are sustainable.

1 cycle: FABS, FCMP, FMOVE, FNEG, FTST
3 cycle: FADD, FINT, FINTRZ, FMUL, FSUB
37 cycles: FDIV
68 cycles: FSQRT

The most common FPU instructions have a 3 cycle latency for FPU register arguments and are 4 bytes. The 68060 fetches 4 bytes per cycle which is 12 bytes per 3 cycles. The instruction buffer is usually filling when executing heavy fp code. FPU instructions with large immediates and displacements and/or integer code executing in parallel may actually drain the instruction buffer but, on average, the 4 bytes per cycle fetch is adequate. A 4 byte per cycle fetch would not be adequate to sustain a pipelined FPU where a FPU instruction is dispatched every cycle.

The 68060 FPU can fetch 8 bytes per cycle from the data cache which is much more common than from memory.

That's cute, but Pentium P5's instruction fetch from the L1 cache is 32 bytes (256 bits) per cycle.

The Pentium P5 decoder stage has 2 port hardware decoders and one port for ROM-based microcode which outputs into two ports. There are four ports in total for the Control Unit.
From the Control Unit, there are ports for the U pipeline, V pipeline, and FPU.

U pipeline is divided into AGU, ALU, and Barrel Shifter.
V pipeline is divided into AGU and ALU.

FPU has its own Control Unit which is divided into FADD, FDIV, and FMUL units.

Warp1260 has access to newer memory speeds for 100 Mhz external bus 68060 Rev 6.

A 100 Mhz 32-bit memory bus is roughly equivalent to a 50 Mhz 64-bit memory bus.

Again, prove 68060 has access to 100 Mhz EDO memory in 1994 and 1996.

My TF1260's SDR memory can reach 100 Mhz, but it didn't exist in 1994 and 1995.

To reflect the real world from 1994 to 1996, 68060 Rev6 @ 100 Mhz needs to have a gimped 50 Mhz memory bus. Warp1260's DDR3 doesn't exist in the 1990s.

For Quake, Pentium Overdrive 83 Mhz (with 16K+16K L1 cache) is about Pentium 75 (with 8K+8K L1 cache) result due to external memory bus issues.


Quote:

This was a reasonable compromise with minimal performance loss used by many practical CPUs to reduce the CPU and memory cost for customers.

Reduce for cost customers? I don't believe your reality distortion field.

The 3MB RAM game console group (3DO, PS1, and Saturn) has a discrete system and video memory pools that exceed the "32-bit" data bus on the PCBs.

Are you game for a 1996 price comparison?

My "far east" PCPartner Socket 7 430VX Baby-AT motherboard is cheaper.

Quote:

Since we have been talking about consoles, the N64 MIPS CPU used a 64-bit CPU with a 32-bit data bus.

The 3MB RAM game console group (3DO, PS1, and Saturn) has a discrete system and video memory pools that exceed the "32-bit" data bus on the PCBs.

N64 has a discrete system and video memory pools that exceed the "32-bit" data bus on the PCBs e.g. 9 bit 250 Mhz Rambus. Rambus has "quad pump" tech.

No 68060 was designed with Rambus's "quad pump" tech.

96-bit memory bus @ 100Mhz would be needed against 9-bit 250 Mhz Rambus's quad pump tech.

N64's cGPU has a geometry co-processor i.e. Reality Signal Processor is another cut-down derivative of the MIPS R4000 which includes a 128-bit Vector Unit i.e. 8 16-bit elements processing capability. Reality Signal Processor has a 4KB+4KB cache.

Amiga Hombre's approach is a fully functional PA-RISC clone CPU with 3D instruction extensions and hardware texture block (blitter texture fill). Nathaniel has a 32-bit/64-bit display memory interface and a 32-bit system memory interface.

Nathaniel's somewhat mirrors 3DO MADAM's discrete system and video memory separation.

Nathaniel is designed to scale up to a 64-bit memory channel for display and a separate 32-bit system memory channel i.e. 96-bit memory interface total from Nathaniel.

Voodoo 1 has a 128-bit bus from two 64-bit chips i.e. 64-bit FBI and 64-bit TMU. Voodoo 1 has a 50 Mhz memory clock.

RIVA 128 had access to 100 Mhz SDR memory chips in 1997. PC100 (SDR 100 Mhz) DIMM in 1998.

100 Mhz 32-bit bus is 75 percent of 66 Mhz 64-bit bus's memory bandwidth.

Quote:

There was a 1993 console with a x86 CPU in Japan called the FM Towns Marty which used a AM386SX that was 32-bit internally with a 16-bit data bus.

FM Towns Marty's 45,000 units is a product failure worse than CD32's 166,000 units sold.

For the price, FM Towns Marty (US $710)'s 386SX-16 doesn't have sufficient power to deliver gaming PC's Doom (and many texture-mapped 3D in 1994).

FM Towns Marty's 2D focus custom chipset was released in the wrong time. This is like A1200's 68EC020-14 Mhz with AA+ chipset.

Sony's PS1 crushed Fujitsu's FM Towns Marty.

FM Towns Marty's 2D focus custom chipset can do the following
- Display up to 720x480
- Bitmap background plane with up to 1024x512 virtual resolution
+- Color palette from 4096, 32768, and 16.7 million
+- Colors on screen from 16, 256, and 32768 (15-bit)
- Sprite foreground plane with 256 colors on the screen from a 32,768 color palette. 1024 16x16 pixel 16 color sprites. This is not arbitrary 256 colors due to 16 color sprites tile limitations.
- Hardware integer zooming
- Backward compatible with FM Towns.

FM Towns desktop computer range has a better success with 500,000 units sold. CPU ranges from 386SX-16 to Pentium 90Mhz Socket 5.

Quote:

The 68060 design was more practical for consoles and embedded use than the high end desktop/workstation Pentium design. The 68060 outperforms the Pentium in integer performance/MHz

Post a 68060 Rev 6 @ 100Mhz Doom demo3 benchmark.

SysInfo already tripped 68060's 4-byte fetch from the L1 instruction cache.

Pentium 90 (430VX with SiS6326 PCI) has 63.35 fps demo3. https://thandor.net/benchmark/32


Quote:

and is not far behind in compiled FPU performance/MHz while it should have been able to easily out clock it for a greater performance advantage.

68060 Rev 6 has a subpar overclocker.

You have forgotten that N64's Reality Signal Processor (62.5 Mhz) is another cut-down derivative of the MIPS R4000 which includes a 128-bit Vector Unit.

N64 has two MIPS R4000-based CPUs i.e. command CPU and geometry CPU-DSP.

MIPS camp's main advantage is outside of Motorola's pricing policies.
MIPS camp's main advantage is outside of Motorola's control policies.

68060 does not have N64's Reality Signal Processor 128-bit vector units!

Quote:

The funny thing is that even without clocking it up and without a 64-bit data bus, the 68060 would have still made a better CPU for a console than a Pentium in the mid-1990s.

Warp1260 has access to +100Mhz capable memory tech that didn't exist from 1994 to 1996.

Prove 100Mhz memory tech from 1994 to 1996.

Quote:

The only thing missing was the economies of scale to make it cheap and that is what a console can do.

FYI, the "3MB memory group game consoles" (3DO, PS1, and Saturn) employ discrete system and video memory bus design. They don't follow Amiga's shared memory bus design.

Prove 100Mhz memory tech from 1994 to 1996.

Quote:

Let's take one more look at just how bad 50MHz is for an 8-stage pipeline CPU.

CPU@max clock rating ~500nm process | pipeline | MHz/stage
ARM710@40MHz 3-stage 13MHz/stage

For the 3DO camp, ARM60 was replaced by PowerPC 602 @ 66 Mhz for 3DO M2.

A particular game console model has a single specification and chip yields must be good for the target specs.

Quote:

PPC601+@120MHz 4-stage 30MHz/stage

PPC601's pipeline length for FPU is 6 stages.
PPC601's pipeline length for load/store is 5 stages.
PPC601's pipeline length for integers is 4 stages.


Quote:

Pentium P54C@120MHz 5-stage 24MHz/stage

Pentium P54C's pipeline length for FPU is 8 stages.
Pentium P54C's pipeline length for integers is 5 stages.

P54CQS, P54CS and P55C share the process node i.e. 350 nm
Pentium P54CQS @ 120 Mhz
Pentium P54CS scales to 200 Mhz

Pentium MMX (P55C) gains an extra stage and reaches 233 Mhz.

Later Mobile Pentium MMX reached 300 Mhz.

Quote:

Alpha 21064@300MHz 7-stage 43MHz/stage

Alpha 21064's pipeline length for FPU is 10 stages.
Alpha 21064's pipeline length for integers is 7 stages.
Alpha 21064's pipeline length for load/store is 7 stages.

https://www.cpu-world.com/CPUs/21064/index.html
Alpha 21064 started from 150 Mhz to 200 Mhz. 21064A started from 233 Mhz to 300Mhz.
To enable higher clock speed, 21064A has implmentation improvements from 21064.
Design changes are needed for higher clock speed.

Quote:

68060@50MHz 8-stage 6MHz/stage

68060's FPU is not fully pipelined.

There's a reason why ColdFire's higher clock speed has ejected certain 68K instructions.

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Lou 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 25-Jul-2024 20:10:19
#272 ]
Elite Member
Joined: 2-Nov-2004
Posts: 4229
From: Rhode Island

Imagine if Commodore had released the A1000 with a 10MHz 65816... Imagine if development continued beyond the 65CE02(8/16) to a 32bit variant...etc..

The 6502 is to a 6800 what a Coldfire is to a 68000. Motorola finally got their head out of their ass and produced a cheaper and more efficient cpu...about 12 years too late!

Imagine if CMOS did to the 68000 what it did to the 6800.
We would/could have had a Coldfire-like cpu in 1983...

In the end, the Amiga is boondoggled to Motorola ... to the point of going down the mostly useless PPC path.

We'd be better off with cheaper and faster CMOS cpus ... and if they had ever upgraded their processes - could have been what AMD is today but with proprietary technology. ARM would have never come to be.

In the end - ARM won. Move on.

Last edited by Lou on 25-Jul-2024 at 08:26 PM.

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cdimauro 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 25-Jul-2024 21:46:11
#273 ]
Elite Member
Joined: 29-Oct-2012
Posts: 4127
From: Germany

@Lou

Quote:

Lou wrote:
Imagine if Commodore had released the A1000 with a 10MHz 65816...

Maybe... no? I don't like horror movies...
Quote:
Imagine if development continued beyond the 65CE02(8/16) to a 32bit variant...etc..

There was a 32 bit variant, but it was never released AFAIR.

Anyway, the glorious 65xx family has given joys, but it's part of the past: it was not a general-purpose architecture, even with its 16 and 32 bit evolutions.

So, no: I don't want to imagine a system like that. As I've said, it would have been an horror movie.
Quote:
The 6502 is to a 6800 what a Coldfire is to a 68000. Motorola finally got their head out of their ass and produced a cheaper and more efficient cpu...about 12 years too late!

Imagine if CMOS did to the 68000 what it did to the 6800.
We would/could have had a Coldfire-like cpu in 1983...

Other times. With the hindsight many things could have changed, and ColdFire isn't really a good example of where to go, IMO, albeit some ideas weren't that bad.
Quote:
In the end, the Amiga is boondoggled to Motorola ... to the point of going down the mostly useless PPC path.

We'd be better off with cheaper and faster CMOS cpus ... and if they had ever upgraded their processes - could have been what AMD is today but with proprietary technology.

See above: cheaper and faster doesn't mean that such CPUs could have been general-purpose.
Quote:
ARM would have never come to be.

Well, it came because the 65xx family wasn't general-purpose enough for the new computation challenges.
Quote:
In the end - ARM won. Move on.

Ehm... won... where? On the embedded market? Absolutely yes.

But there are other markets.

P.S. I've seen your passion for the 65xx family. I've started with them and I liked... at the time. But they are nowhere comparable to a 68000, whatever incarnation you might consider.

BTW, the "benchmark" that you've reported some time ago (I don't recall the thread now) with the comparison of some architectures (65xx and 68000 included) is one the worst ever seen: pure crap.

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Hammer 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 26-Jul-2024 2:14:42
#274 ]
Elite Member
Joined: 9-Mar-2003
Posts: 6179
From: Australia

@Lou

Quote:

Lou wrote:
Imagine if Commodore had released the A1000 with a 10MHz 65816... Imagine if development continued beyond the 65CE02(8/16) to a 32bit variant...etc..

The 6502 is to a 6800 what a Coldfire is to a 68000. Motorola finally got their head out of their ass and produced a cheaper and more efficient cpu...about 12 years too late!

Imagine if CMOS did to the 68000 what it did to the 6800.
We would/could have had a Coldfire-like cpu in 1983...

In the end, the Amiga is boondoggled to Motorola ... to the point of going down the mostly useless PPC path.

We'd be better off with cheaper and faster CMOS cpus ... and if they had ever upgraded their processes - could have been what AMD is today but with proprietary technology. ARM would have never come to be.

In the end - ARM won. Move on.


Commodore should have developed 6510 into 32-bit variant 65032. 6510 already has 16-bit 64K memory address space. 65816 is "braindead" like 80286 for 32-bit desktop OS.

ARM and ARC (Argonaut RISC Core) are the response against slow 65K's R&D road map issues. ARM and ARC are the "cheap RISC" that replaced the cheap 65K series CPUs.

Last edited by Hammer on 26-Jul-2024 at 02:16 AM.

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Lou 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 26-Jul-2024 2:31:18
#275 ]
Elite Member
Joined: 2-Nov-2004
Posts: 4229
From: Rhode Island

@cdimauro

Crap eh? Many an actual developer from the 80's and 90's will tell you the same thing.
Also - 680x0 was second only to the VAX in terms of the complexity of its instruction set...

I detect bitterness. Oh well. Someday you will realize 8bit processors aren't limited to 64k thanks to MMUs and the like.

Fyi:
A simple adapter can turn a C128 into a C256 and there are schematics for 1MB...
https://www.youtube.com/watch?v=hrtqsCeGGl0
Putting it to use:
https://www.youtube.com/watch?v=Areq8K_ia9Y

Phones are the new affordable PC. PCs are slowly being regulated to businesses again.
...so yes - ARM did win.

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Hammer 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 26-Jul-2024 4:16:07
#276 ]
Elite Member
Joined: 9-Mar-2003
Posts: 6179
From: Australia

@Lou

https://www.kotaku.com.au/2024/05/pc-gaming-is-growing-faster-than-consoles-data-shows/
PC Gaming Is Growing Faster Than Consoles, Data Shows.

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Hammer 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 26-Jul-2024 4:24:36
#277 ]
Elite Member
Joined: 9-Mar-2003
Posts: 6179
From: Australia

@cdimauro

Quote:
Any data for them?


Example,

The cost breakdown for PS4
https://www.engadget.com/2013-11-19-ps4-costs-381-to-make-according-to-hardware-teardown.html

AMD's Liverpool APU's cost is $100.00.

Using US inflation cost calculator. https://www.minneapolisfed.org/about-us/monetary-policy/inflation-calculator

$100.00 in Y2012 is about $62.92 in Y1993.

Commodore Hombre's two chips solution has $40 cost estimate.

Factoring US inflation between 1993 and 2012, the cost structures remained similar.

Memory remained to be the costly components for either CD32/A1200 and PS4.

The package cost for 486DX4's $23 to $28 are within $40 to $60 level, hence it's just the profit expectation policy for Intel or AMD i.e. this is shareholder related matter.

Since Pat's Intel is aiming for the Next Xbox contract, it's most likely is aware of a typical game console's cost structure. It comes down to the "value added" for the given money. Microsoft would be looking for "bang per buck" value added features.

Both Intel and AMD are competing in the handheld gaming PC market which is not strictly "business PC".

For expanding PowerPC's usage, IBM is willing to sit down and hash out a game console design win e.g. 3DO M2.



Last edited by Hammer on 26-Jul-2024 at 04:44 AM.
Last edited by Hammer on 26-Jul-2024 at 04:26 AM.

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cdimauro 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 26-Jul-2024 4:32:00
#278 ]
Elite Member
Joined: 29-Oct-2012
Posts: 4127
From: Germany

@Lou

Quote:

Lou wrote:
@cdimauro

Crap eh?

Not crap: PURE crap.

Making a benchmark to "measure" (SIC!) the performance of computers/architectures using just ONE single instruction is the dumbest idea which I've seen.

This guy deserves the Ig Nobel Prize.
Quote:
Many an actual developer from the 80's and 90's will tell you the same thing.

Well, do you know how the IQ is measured? It's a Gaussian:



So, not only IQ 100 is the average, but the chart shows also that there are people which are located to the left side of IQ 100 and people which are on the right side.

You can guess where such developers should be located...
Quote:
Also - 680x0 was second only to the VAX in terms of the complexity of its instruction set...

No, there are other architectures which are way more complex than the 680x0.

The AT&T one, for example. And it's not the only one.

That's because it was common having ISAs with instructions having multiple operands with the possibility to define any addressing mode for such operands (which means: they can all access to memory).
This was super-powerful and made the ISA orthogonal (and with very good code density), but paying a BIG price on decoding such instructions.
Which is the reason why they went to the dust when processors started pushing on pipelining the instructions execution.

However, an ISA with cleaver instruction encodings can easily overtake those issues.
Quote:
I detect bitterness. Oh well.

Which bitterness? As I've said, I've loved the 65x0 processors. The 6510 was the first processor which I've coded in machine language, and then in assembly. I've spent years tinkering with that and I've enjoyed it a lot.

However, when I had the chance to study and then use the 68000 of my first Amiga, I was like this:


Quote:
Someday you will realize 8bit processors aren't limited to 64k thanks to MMUs and the like.

Fyi:
A simple adapter can turn a C128 into a C256 and there are schematics for 1MB...
https://www.youtube.com/watch?v=hrtqsCeGGl0
Putting it to use:
https://www.youtube.com/watch?v=Areq8K_ia9Y

Guy, I had a C128 (my second computer, after the Plus/4 which I had for just one month) and I already knew that was expandable to 256kB even before that I bought it...

I was also aware of the RSU unit for further expand the memory and of experiments with the 65WD816.

This doesn't change a single comma of what I've said: such processors & systems aren't enough general-purpose.
Quote:
Phones are the new affordable PC.

Well, no: they deserve DIFFERENT purposes & usages.
Quote:
PCs are slowly being regulated to businesses again.
...so yes - ARM did win.

Are... being -> Future?

Let's talk WHEN ARM processors have >50% of the PC market...

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cdimauro 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 26-Jul-2024 4:38:56
#279 ]
Elite Member
Joined: 29-Oct-2012
Posts: 4127
From: Germany

@Hammer

Quote:

Hammer wrote:
@cdimauro

Quote:
Any data for them?


Example,

The cost breakdown for PS4
https://www.engadget.com/2013-11-19-ps4-costs-381-to-make-according-to-hardware-teardown.html

AMD's Liverpool APU's cost is $100.00.

Using US inflation cost calculator. https://www.minneapolisfed.org/about-us/monetary-policy/inflation-calculator

$100.00 in Y2012 is about $62.92 in Y1993.

The context was: consoles of the time (1990-1993).

BTW, when this (sub)part of the discussion started it was about the final prices of such consoles and not their BOMs.
Quote:
Commodore Hombre's two chips solution has $40 cost estimate.

That was a lot for the time, looking at the market target. I doubt that the CD64 would have been profitable for Commodore.

Anyway, it was too late.
Quote:
Factoring US inflation between 1993 and 2012, the cost structures remained similar.

Memory remained to be the costly components for either CD32/A1200 and PS4.

Yes, but the 1200 had 2MB of RAM and it was a good amount for such time & market.

The CD32 deserved a bit more to address 3D games, but they came & exploded only when Doom was introduced. And without crystal balls, it wasn't possible to figure out this big market change.

Last edited by cdimauro on 26-Jul-2024 at 05:06 AM.

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Hammer 
Re: DoomAttack (Akiko C2P) on Amiga CD32 + Fast RAM (Wicher CD32)
Posted on 26-Jul-2024 5:52:38
#280 ]
Elite Member
Joined: 9-Mar-2003
Posts: 6179
From: Australia

Quote:

@cdimauro
The context was: consoles of the time (1990-1993).

Both Dr Ed Helper and Ken Kutaragi arrived at 1 million transistor budget for the game console's main compute, visual and audio components.

https://segaretro.org/History_of_the_Sega_Saturn/Development
For the Saturn project, Sega has considered 68030 CPU which could indicate the price range.

For 1993, 68EC030's and 68030's price ranges are known from DataQuest reports.

Actual BOM costs are behind NDA.

Quote:

@cdimauro
Yes, but the 1200 had 2MB of RAM and it was a good amount for such time & market.

I recall, A1200's 2MB Chip RAM has a $52 price range.

During CD32's development, Psygnosis warned Mehdi Ali of the competition.

Quote:


From Commodore the Inside Story, The Untold Tale of a Computer Giant by David John Pleasance

CD32

As Commodore’s engineers designed the basic specifications of the CD324 – which appeared to be, for the first time ever, the subject of a well-planned and considered product launch – we managed, under strict non-disclosure agreements, to seed CD32 development
machines into most of the major games software development houses. They had begun writing games especially designed to utilise the full capabilities and features this 32-bit CD-based machine had to offer so that at the planned launch – scheduled to be in late
spring/early summer of 1994 – there would be a plethora of fantastic games launched at the same time.

As a result of this, I was asked by Ian Hetherington (cofounder, with Jonathan Ellis, of Psygnosis) to arrange a meeting with Mehdi Ali at their studios in Liverpool.

Mehdi was not very happy with the idea, but I ignored his moaning and drove him there.
Ian explained to Mehdi that with a few seemingly quite modest design changes, the CD32 could have an incredible boost in performance at very marginal additional cost.


He also pointed out the benefits it would give developers like Psygnosis and other major players in the industry, who would find it easier to produce even better-quality products and enhance the reputation of the CD32 and the games publishers – a genuine ‘win-win’. Ian
had not requested any financial reward for this – it seemed he simply wanted to offer considerably improved games performance and to be credited for his
contribution.

Well, it went exactly as expected. Mehdi was rude and ignorant, and clearly had no idea what Ian was talking about. But instead of just admitting that, he more or less turned on Ian, as though he ‘must be crazy telling us how to design our computers!’ I ushered Mehdi out of the
building feeling very ashamed, and it was quite a while before I plucked up the courage to talk to Ian again.

Luckily for me, Ian had realised what kind of a person Mehdi Ali was and held no bad feelings towards me.

The real sting to this story is that Psygnosis subsequently sold their company to Sony Computer Entertainment Europe, with Ian Hetherington being made head of Sony PlayStation Europe – and I often wonder to myself: ‘If Mehdi Ali had not been such an obnoxious prick, would Commodore have had that technology?’



Quote:

@cdimauro

The CD32 deserved a bit more to address 3D games, but they came & exploded only when Doom was introduced. And without crystal balls, it wasn't possible to figure out this big market change.

Commodore is made aware of chunky pixel since 1990's Wing Commander which made an impact in COMMODORE - The Final Years by Brian Bagnall.



Quote:

From COMMODORE - The Final Years by Brian Bagnall,

The Gail Problem

Jeff Porter had laid the groundwork for the C65 marketing push, including a plan to attract a large number of launch titles. “That’s marketing 101 on how to make the C65 successful,” he says. “Get the third party software developers on your side. And how do you do that? By getting the people who work for Commodore on your side to talk to the third party developers.”

Porter needed to attract some of the top C64 developers in the US over to the C65 platform. At the time there were many software houses who had made their name on the C64, including EA, Activision, Broderbund, Epyx, Origin, and Access Software. In the latter part of 1990, these companies started embracing the PC world as new video and sound cards made games more exciting. Games such as Wing Commander came out that turned the heads of video gamers.


Note why Wing Commander was selected as part of the game bundle for CD32.

C65's "mooooore colors" is a distraction.

Doom wasn't the only chunky pixel game from the PC's 1992-1993.

The warning signs for gaming PC's rise was in 1990 and SNES has chunky pixel Mode 7 since 1990.

Gaming PC's flood of texture-mapped 3D game releases in 1994 would have been developed in the 1991 to 1993 time period. Communicating with major game developers would help.

If your viewpoint is based on retail release, it's too late. You haven't factored industrial espionage and industrial intelligence gathering.

Like many Amiga gamers, my 1st gaming PC was in Xmas Q4 1992. I have noticed Wing Commander since 1990.

Last edited by Hammer on 26-Jul-2024 at 06:15 AM.
Last edited by Hammer on 26-Jul-2024 at 06:13 AM.
Last edited by Hammer on 26-Jul-2024 at 06:12 AM.
Last edited by Hammer on 26-Jul-2024 at 06:09 AM.
Last edited by Hammer on 26-Jul-2024 at 06:02 AM.
Last edited by Hammer on 26-Jul-2024 at 05:57 AM.
Last edited by Hammer on 26-Jul-2024 at 05:55 AM.

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