@AmigaMac

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AmigaMac wrote: @Hammer Thanks for responding with that bit of history.

Bit of history?!?!

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All the way, with 68k

Hammer Quote:

I suspect Vortex86EX2 dual core is used for Space X's Falcon 9. Falcon 9 has 3 dual core x86 processors running an instance of Linux on each core. From https://www.vortex86.com/products/Vortex86EX2 Vortex86EX2 dual core can run an instance of Linux on each X86 core and supports ECC memory. ECC memory support is a premium feature on Intel X86 CPU offerings. ECC memory support is semi-standard on AMD's AM4 and AM5 offerings since it's dependant on the motherboard's brand. Space X Falcon 9 is not legacy embedded.

The DM&P SoCs are still more specialized/niche embedded than mainstream. ECC memory support, an older chip fab process and an extended temperature operating range may have been advantages for high altitudes and rockets. The catalogue below mentions the extended temp support as well as giving the following info on the Vortex86 CPU core.

https://www.qproducts.sk/files/ICOP-catalogue.pdf Quote:

Vortex86 family integrates a high-performance processor that supports x86 instruction set with 3 integer units, 3-way superscalar architecture, and a fully pipelined floating point unit. In addition, the processor is a power-efficient design that optimizes the power consumption for information appliance applications

The Vortex86 CPU core sounds similar to the mP6 core.

https://en.wikipedia.org/wiki/MP6#Design Quote:

The mP6 made use of the MMX instruction set and had three MMX pipelines which allowed the CPU to execute up to three MMX instructions in a single cycle. Its three integer units made it possible to execute three integer instructions in a single cycle as well and the fully pipelined floating point unit could execute up to two floating-point instructions per cycle. To further improve the performance the core utilized branch prediction and a number of techniques to resolve data dependency conflicts. According to Rise, the mP6 should perform almost as fast as Intel Pentium II at the same frequencies.

Other info describes the superscalar Vortex86 CPU core pipeline as 8-stage, the same as the mP6. The mP6 core area and power were likely high for embedded use but maybe the DM&P license for the mP6 core expired or the HDL code was a mess. The Vortex86 core was clocked low which is an advantage for embedded use but poor for marketing to x86 retro users and even some embedded customers do not understand the advantages of high performance at a lower clock speed (68060@50MHz embedded customers understood). DM&P replaced the mP6 core with what is likely a modified 6-stage scalar Cyrix 5x86 CPU core in successor Vortex86 SoCs.

Hammer Quote:

Vortex86DX doesn't support MMX. Vortex86MX has MMX support. Vortex86DX3 has MMX and SSE support. This Vortex86DX3 SKU has 999 Mhz clock speed https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=63347 Vortex86EX2's master CPU core has MMX, SSE, SSE2, SSE3, SSSE3 and NX support and it's produced using the 65 nm manufacturing process. This Vortex86EX2 SKU has 600 Mhz clock speed. https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=72324 For Vortex86DX @ 933 Mhz https://www.dr-lex.be/hardware/btplug_review.html Speed The next thing I tested is how well the Vortex86DX @933MHz performs, as well as the system as a whole. First of all, I ran a simple benchmark program of my own that counts how many times various calculations and data-processing operations can be executed during a fixed time. I have been running that program on many different machines so this allowed me to conclude that overall, the BTplug is somewhat comparable to a fast Pentium II or a slow Pentium III-based PC. It heavily depends on the task however, for convolving an image the Vortex86 is slower than anything I've benchmarked yet, but for creating a word histogram from text it is comparable to a Pentium 4. Emerging small packages in Gentoo is perfectly feasible, but you won't want to compile a kernel on the BTplug if you're in a hurry. A note about the Vortex86DX: I have found rumours on some forums that the Vortex86DX would support MMX, but this is untrue. The cpu flags in /proc/cpuinfo only mention fpu tsc cx8, and a test program to check the availability of MMX fails. The newer Vortex86MX does support MMX.

SIMD support is not all that was lost when changing Vortex86 SoC CPU cores from the mP6 core to the Cyrix 5x86 core.

https://en.wikipedia.org/wiki/Cyrix_5x86#Design Quote:

The chip featured near-complete support for i486 instructions, but very limited support for Pentium instructions.

I suspect that the scalar Cyrix 5x86 CPU core is a better design than the superscalar mP6 core and that the HDL code is in better shape making it easier to modify. The scalar Cyrix 5x86 CPU core was later and more advanced than the scalar 80486 and 68040 cores. The scalar 6-stage Cyrix 5x86 CPU core is similar to the in-order Pentium class superscalar 7-stage Cyrix 6x86 but with one execution pipeline and a pipeline stage of decoding and dispatch/issue removed. This is similar to what was planned for the "68060Lite".

https://websrv.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/080502.pdf Quote:

The ’060 was designed from the beginning as a modular processor. It can be stripped down or enhanced in various ways to meet price and performance needs. Versions proposed within Motorola, but not guaranteed to be put into production, include: o 68060Lite - single integer pipeline, no FPU, cache sizes reduced, similar to 68LC040 but less costly. o 68060S - instruction set reduced but still compatible with 68000, smaller caches, may integrate customer specific logic. o 68060+ - undisclosed architectural enhancements that increase performance 20-30% independent of clock frequency. Process improvements will bring further speed gains and, perhaps more important, cost reduction.

The "68060Lite" was never "put into production" but the scalar ColdFire V4 is practically a ColdFire V5Lite version of the superscalar ColdFire V5 which is similar to the superscalar 68060 design. The ColdFire V4 and V5 pipelines are the same, except for the V5 2nd execution pipeline, which may indicate decoding and dispatch are simpler on ColdFire due to better orthogonality. The Cyrix 5x86 instruction set is reduced from Pentium to 486 ISA kind of like ColdFire is reduced from 68k to ColdFire except Motorola performed more castration and made the mistake of not preserve 68k compatibility. A CF5407 SoC with ColdFireV4@162MHz CPU core using a 220nm process already typically dissipated less than 1W of power while delivering 1.6 DMIPS/MHz. Even the 0.8 DMIPS/MHz ColdFire V3 core destroyed the AMD486DX5 using the same chip process.

https://halfhill.com/mpr/2000/142001.pdf Quote:

Feature | CF5307/CFv3 | AMD486DX5 Voltage 3.3V 3.3V Process 350nm 350nm Die_Size 27mm^2 43mm^2 Typical_Power 0.79W 2.75W L1cache U8kiB U16kiB Performance_Efficiency 0.8DMIPS/MHz 0.4DMIPS/MHz Power_Efficiency 94.6DMIPS/W 21DMIPS/W Price_Efficiency 4.4DMIPS/$ 2.1DMIPS/$ Price(10k) $14.95 $26.80

ColdFire V3 completely dominated the AMD486DX5 in PPA like the 68060 owned the Pentium. ColdFire V3 performance/MHz is double that of the AMD486DX5 using roughly 1/4 the power and then the ColdFire V4 doubled performance again. The ColdFire even has a handicap by using all auto layout tools.

https://halfhill.com/mpr/2000/142001.pdf Quote:

The larger caches are the biggest reason that the die didn’t shrink dramatically. Another reason is starkly visible in Figure 2, the die photo. ColdFire is the only family of processors from Motorola that’s entirely synthesized from high-level models with automated design tools. There’s no custom circuit layout at all. Compiled chips are bigger, slower, and less power-efficient than full-custom designs, but they are much quicker and cheaper to create. Where a hand-packed design typically has neat blocks of function units inside a Piet Mondrian grid of buses, the 5407 has an amorphous mass of compiler-generated circuits on a Jackson Pollock canvas of silicon. The only semblance of order comes from the caches and on-chip memories around the periphery of the die. They’re compiled too, but SRAM arrays obediently fall into dense rows and columns, even without a guiding hand.

The scalar Cyrix 5x86 design is no doubt a better design than the scalar Intel 80486 but the x86 ISA is a major handicap and reducing power of small x86 cores is challenging. Scalar CISC core designs can still be more powerful than RISC core designs as instructions like ADD (mem),Rn can be executed as one instruction with single cycle throughput where RISC cores are typically load+change-use-delay+add which has a 5 cycles latency in the case of this sequential code on a Cortex-A53 core. DM&P was able to make more changes to the Cyrix 5x86 core too starting with what looks like splitting the unified L1 cache into separate instruction and data caches, reducing the data bus from 32-bit to 16-bit and modernizing the memory support.

SoC | CPU core | stages | ISA | L1 cache | L2 cache | data bus | memory
Vortex86 mP6 8-stage Pentium+MMX 8kiB_I+D none 64-bit SDRAM
Vortex86DX 5x86 6-stage 486 16kiB_I+D 256kiB 16-bit DDR2
Vortex86DX2 5x86 6-stage 486|586+MMX? 16kiB_I+D 256kiB 32-bit DDR2
Vortex86DX3 5x86 6-stage 486|586+MMX? 32kiB_I+D 256kiB 32-bit DDR3

DM&P probably would have been better off if they started off with the Cyrix 6x86 which is superscalar and has Pentium support but it would have used more power and area which may have been a problem for their markets.

https://www.cpushack.com/2010/10/07/the-rise-of-the-vortex86-embedded-x86/ Quote:

The Vortex86DX is a fully capable x86 processor. It is perfect for very small PC applications and embedded designs where x86 code is required. The PMX-1000 can run at up to 1GHz and adds IDE support, graphics, and HD-Audio (much like the original SiS550. While technically an embedded CPU the PMX-1000 is fully capable of running Windows and other x86 programs. eBox (part of DM&P) makes many small form factor, fanless, and sealed PCs based on it. It runs on a rather small 2.2Watts at 800MHz, a third the power, and 4 times the speed of the original Rise mP6.

It sounds like the Vortex86DX already underclocked the SoC from 1000MHz to 800MHz for "small form factor, fanless, and sealed PCs", likely due to high power draw and heat. This is why the 68k was number 1 in the 32-bit embedded chip market in 1997 by volume while x86 was number 6 behind number 4 ARM. The x86 volumes still beat number 7 PPC but what did Motorola expect when code density is so important for the embedded market that ARM moved in the other direction of trading their fat original ARM ISA for the ARM Thumb ISA with 68k like code density but not performance. The rest is history and Motorola/Freescale/NXP now pays royalties for ARM.

RISC Volume Gains But 68K Still Reigns
https://websrv.cecs.uci.edu/~papers/mpr/MPR/19980126/120102.pdf

The Vortex86 enhancements and modernizations are the same type of enhancements that a 68060 SoC ASIC would require. A superscalar 68060 core would likely use less power than a scalar Vortex86 core using the same process. The 68060 HDL code was designed to be modular and configurable so hopefully it would be more like the Cyrix 5x86 HDL code than perhaps the mP6 HDL code to modify. Even with auto layout tools for quickly moving to new chip processes, the 68060 is likely to remain as competitive as the ColdFire which also used auto layout to dominate the AMD486DX5. Of course, even a modernized scalar CPU core like the Cyrix 5x86 outperforms anything and everything the 68k Amiga uses, including emulated and FPGA 68k CPU cores. If the scalar Cyrix 5x86 continues to be modernized, it will likely outperform every PPC OoO core ever designed because that is what happens when the silicon and tech ages. DM&P x86 cores are not very competitive in the embedded market and they rarely update their cores and SoCs but compatibility no doubt earns them more business than PPC AmigaNOne hardware on old silicon that will never be updated.

By the way, Quake had better performance with the Vortex86DX 16-bit data bus than with the Vortex86 64-bit data bus. It is memory bandwidth that matters when streaming data from memory and there are other factors than the data bus width and even memory bandwidth. The Vortex86DX led in the Doom and 3DBench benchmarks with the 16-bit data bus. The 68060 32-bit data bus was practical.

https://web.archive.org/web/20030104144558/http://worldwide-web-design.com/5x-tb.html Quote:

Two facts were fundamental in identifying features for the 5x86: the 32-bit architectural standard of x86 technology, and the average instruction length for existing 8/16-bit and 32-bit code. These facts enabled Cyrix to reduce the bus width required to handle most data and code transactions to 32 bits. To exploit the inherent parallelism, the 5x86 utilizes decoupled units interconnected with multiple 32-bit, split-transaction buses.

The advanced Cyrix 5x86 core design can often queue data bus transfers when the bus is busy using "decoupled units" rather than halting the execution pipeline(s) like earlier scalar CPU cores (e.g. load and store buffers). The 68060 does the same thing. Also, better code density reduces the instruction memory traffic leaving more bandwidth available for data traffic which is what I tried to explain to you once. I believe this is what they are trying to explain above when they talk about "average instruction length". Code density is actually a better way to put it as the average size of instructions times the number of instructions is important for memory traffic. The x86 average instruction length is smaller than for the 68k when optimizing for size and close when optimizing for performance, but 68k code uses fewer instructions and has better code density. The x86-64 average instruction length has increased dramatically, especially when optimizing for performance, but the number of instructions have decreased partially offsetting it with an overall code density decline. I do not know if you do not listen to me, do not believe me or forget what I say.

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@matthey

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By the way, Quake had better performance with the Vortex86DX 16-bit data bus than with the Vortex86 64-bit data bus.

Vortex86DX SoC has 16bit DDR2 with a 333 Mhz clock speed for the external memory bus. 333 Mhz DDR2 translates into 666 MT/s with 1,332 MB/s potential.

Vortex86DX SoC's CPU I/O with integrated NB (northbridge) is internal. 68060 is not SoC. Cache coherence NB competence is one of the major features of the P5 Pentium generation.

AMD/Intel x86 CPUs with dual channel 64bit DDR2 (128-bit DDR2) with 666 MT/s is faster.

The original Vortex86 (rename SiS 551) model used in benchmark https://www.vogons.org/download/file.php?id=109132&mode=view was a 166 Mhz model.

SiS 551 with 100 Mhz 64bit bus has 800 MB/s potential. SiS 551 used SDRAM DIMM (64bit).

DDR2 for mainstream PCs is in the Intel Core 2 era.

Warp1260's DDR3 is limited by 68060's 32bit 100 Mhz external bus while Rise mP6 has 100 Mhz 64bit FSB on Super Socket 7.

Memory bandwidth = bit width x clock speed.
Memory bandwidth = bit width x effective data transfer rate.

This is basic computer science 101.


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SoC | CPU core | stages | ISA | L1 cache | L2 cache | data bus | memory Vortex86 mP6 8-stage Pentium+MMX 8kiB_I+D none 64-bit SDRAM Vortex86DX 5x86 6-stage 486 16kiB_I+D 256kiB 16-bit DDR2 Vortex86DX2 5x86 6-stage 486|586+MMX? 16kiB_I+D 256kiB 32-bit DDR2 Vortex86DX3 5x86 6-stage 486|586+MMX? 32kiB_I+D 256kiB 32-bit DDR3

From https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=63347
Vortex86DX3 supports MMX and SSE. Extra SIMD INT/FP pipelines for SSE can be added for improved multimedia and pack math FP32/FP64 use cases.

Vortex86DX3's CMOV instructions were introduced in P6 (i686) family processors.
Vortex86DX3's CMPXCHG8B instruction was introduced in P5 (i586) family processors.

https://wiki.gentoo.org/wiki/User:Immolo/ebox-3350dx3
Vortex86DX3's feature flags: fpu pse tsc msr cx8 apic sep pge cmov mmx fxsr sse cpuid
bogomips: 1999.77 from 999.904 Mhz


IBM PPE was a simplified dual-issue in-order PowerPC core with VMX128 SIMD.

Intel Atom Bonnell microarchitecture was a simplified dual-issue in-order IA-32 and X64 (some models) with SSSE3 SIMD.

Quake benchmark doesn't use SSE. Original Xbox-era games made SSE mandatory.


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ColdFire V3 completely dominated the AMD486DX5 in PPA

https://www.nxp.com/products/MCF530X
ColdFire V3 core delivering up to 75 (Dhrystone 2.1) MIPS @ 90 MHz.

https://ieeexplore.ieee.org/document/805823
MCF5307 (ColdFire V3) was released in about 1999.

Where's ColdFire V3's FPU and MMU? Another "EC" from Freescale.

ColdFire V3 can't run desktop-grade PMMU Linux.

AMD486DX5 has mainstream 3D texture-mapped games while ColdFire V3 is a barren wasteland.

Am486DX5-133V16BGC was introduced in 1996 as a budget X86 PC CPU below the budget Am5x86 models.

StrongARM SA-110 has PMMU that can run desktop-grade Linux.

ColdFire V4 was released in the year 2000 with production ramped in Q3 2000.

For the year 2000, budget Coppermine Celeron (e.g. original Xbox release) and K8 Duron (e.g. Xbox prototype) CPUs beat ColdFire V4! K7 Duron was released in the year 2000. K6-III acted as AMD's budget x86 CPU line during K7 Athlon Slot A before K7 Duron Socket A.


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like the 68060 owned the Pentium.

False e.g. Pentium's Quake results beat 68060.

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ColdFire V3 performance/MHz is double that of the AMD486DX5 using roughly 1/4 the power and then the ColdFire V4 doubled performance again. The ColdFire even has a handicap by using all auto layout tools.

Meaningless for the gaming market.

Am486DX5-133V16BGC was introduced in 1996 as a budget X86 PC CPU below the budget Am5x86 models.

AMD released the K5 family in March 1996 and Quake was released in July 1996. Quake's release has culled many CPUs from the desktop computer market. AMD K6 MMX was released in April 1997. Cyrix 6x86 was culled from gaming PC builds and pushed them into budget niches.

You didn't factor in the product release schedules.

Intel Coppermine 128K L2 cache @ 733 Mhz has a design win for the original Xbox game console.

The original Xbox and NVIDIA nForce 2 Deluxe PC motherboards used Motorola 56300-based DSP under NVIDIA's SoundStorm brand. When MS funding for Xbox dried up, NVIDIA dropped Motorola 56300-based DSP citing high-cost issues for K8 nForce 3 chipsets.

NVIDIA nForce 2 non-Deluxe motherboard models don't have Motorola 56300-based DSP.
56300-based DSP for the nForce 2 Deluxe was normally driven by software code largely derived from the 3D audio middleware company Sensaura.

That's year 2000 era embedded hardware with 3D gaming use case i.e. original Xbox's components vs Cold Fire V4.

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_________________
Amiga 1200 (rev 1D1, KS 3.2, PiStorm32/RPi CM4/Emu68)
Amiga 500 (rev 6A, ECS, KS 3.2, PiStorm/RPi 4B/Emu68)
Ryzen 9 7950X, DDR5-6000 64 GB RAM, GeForce RTX 4080 16 GB

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by Hammer on 22-Jan-2025 1:35:02 @amigang 1. A standalone FPGA Amiga AGA clone with an A1200 CPU edge connector for any current and future A1200 accelerator cards. 2. A standalone Pi HAT-based middle board for Nanomig (cheap FPGA Amiga chipset clone) and RPi CM4 (for Emu68). Middle board with PCIe slot.

1. The product is a customized AGA Emulation platform featuring an integrated standalone FPGA, designed to support the original Amiga A1200 CPU architecture and accelerator cards interface via its edge connector. It's aimed at preserving compatibility with existing hardware while also being future-proof for new compatible components.

2. This product offers a custom middle board that supports both Nanomig FPGA chipset clones (a low-cost alternative to the original Amiga architecture) and RPi CM4, which is tailored towards emulating Emu68k systems like those used by various Unix-based operating systems. It includes PCIe connectivity for en

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by Hammer on 15-Feb-2025 21:31:51 @matthey Quote: By the way, Quake had better performance with the Vortex86DX 16-bit data bus than with the Vortex86 64-bit data bus. Vortex86DX SoC has 16bit DDR2 with a 333 Mhz clock speed for the external memory bus. 333 Mhz DDR2 translates into 666 MT/s with 1,332 MB/s potential. Vortex86DX SoC's CPU I/O with integrated NB (northbridge) is internal. 68060 is not SoC. Cache coherence NB competence is one of the major features of the P5 Pentium generation. AMD/Intel x86 CPUs with dual channel 64bit DDR2 (128-bit DDR2) with 666 MT/s is faster. The original Vortex86 (rename SiS 551) model used in benchmark…

The Vortex86 SoC, particularly the mP6 and DX series models, had a strong performance advantage over their contemporaries like SiS 551 with its slower SDRAM DIMM (64-bit), due to faster DDR2 memory buses. However, while they were ahead in terms of raw CPU core speed and cache sizes compared to the mP6's original Vortex86 model at a lower clock rate, their performance was still not on par with later AMD/Intel x86 processors that used dual-channel DDR2 memory or even DDR3. The ColdFire V4 did offer significant improvements over its predecessor but struggled to compete in the gaming