Just discovered this project:

http://bjump.org/

I wondered if it might be helpful in transforming FPGA-based Amigas (Vampire, etc...) into an ASIC. It seems like it could speed up the ASIC design process. Anyone got any thoughts on this?

On a tangentially related note, I've often thought this was a great game idea:

http://hol.abime.net/51

Oh and in case ASICs seem out of reach...

https://spectrum.ieee.org/tech-talk/computing/hardware/lowbudget-chip-design-how-hard-is-it

"How much would that custom ASIC cost to make? Estimating the cost of mask and chip fabrication is difficult, because price lists are confidential. But stories I’ve heard suggest that a simple ASIC (say one that is a few square millimeters in size, fabricated using the 250-nm technology node) might cost a few thousand bucks for a couple dozen samples."

For reference, the 250nm node was used for CPUs that went to around 550MHz:

https://en.wikipedia.org/wiki/AMD_K6-2

It was also the processor node used for the Dreamcast CPU and GPU, and that was no slouch:

https://www.youtube.com/watch?v=b4Oe1Kss_AQ

Last edited by HenryCase on 12-Oct-2018 at 08:50 PM.

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HenryCase wrote: Just discovered this project: http://bjump.org/ I wondered if it might be helpful in transforming FPGA-based Amigas (Vampire, etc...) into an ASIC. It seems like it could speed up the ASIC design process. Anyone got any thoughts on this?

There are plenty of open hardware resources and allies available. Some people and businesses trying to make money off a product don't understand the advantages of open hardware much like open software. I think Gunnar is one of those of people who thinks he is more likely to make money off of closed hardware (Jens Kuenzer wanted to open up the N68050). He obviously believes the Apollo core is FPGA only as he has highly optimized the CPU design, HDL and ISA for FPGA. This in contrast to a CPU core designed for FPGA and ASIC.

Quote:

HenryCase wrote: Oh and in case ASICs seem out of reach... https://spectrum.ieee.org/tech-talk/computing/hardware/lowbudget-chip-design-how-hard-is-it "How much would that custom ASIC cost to make? Estimating the cost of mask and chip fabrication is difficult, because price lists are confidential. But stories I’ve heard suggest that a simple ASIC (say one that is a few square millimeters in size, fabricated using the 250-nm technology node) might cost a few thousand bucks for a couple dozen samples." For reference, the 250nm node was used for CPUs that went to around 550MHz: https://en.wikipedia.org/wiki/AMD_K6-2 It was also the processor node used for the Dreamcast CPU and GPU, and that was no slouch: https://www.youtube.com/watch?v=b4Oe1Kss_AQ

The CEO I was talking to about using old under-utilized die processes for mass produced IoT was using 180nm or 152nm die size giving a per unit cost of less than $.03 U.S. for mass production of a SoC CPU capable of running a TCP/IP stack. The mask was about $25000 U.S. with a wafer giving about 3500 CPUs for $1800 U.S with a minimum of around 12-18 wafers required. This information would be from about 2016. The design, HDL programming, layout and verification of a core are the expensive parts of creating a core and this is where professionals are worth their high costs.

The CEO's first embedded target was the 68k (CPU32 on 68332) and "can still program assembler in 68k like the wind compared to SH". He showed interest in the 68k saying, "if there is traction with a 68k, and a core can be made that is small and portable, we’re all for that. Especially something that can do fairly arbitrary superscalar parallel pipelines, and works well SMP (locking primitives, cache control, etc)". Unfortunately, he wants open hardware and an ASIC ready core and build system which disqualifies the Apollo core. Gunnar was optimizing away for performance in an FPGA while I was saying to keep the core and ISA flexible for an ASIC while improving code density for embedded. The original reason I contacted the CEO was because of a slide he showed with Dr. Vince Weaver's old cold density chart which had changed. The 68k went from 7th best to 1st in code density for Linux capable ISAs while his SH-3 went from 4th to 10th with other performance limiting stats I had compiled (too many instructions and too much memory traffic). The same slide also says in reference to code density, "There *are* other metrics, but none actually matter more (unless something is broken)". This is understandable as they tried to use LEON SPARC before but the instruction fetch was eating their memory bandwidth due to poor code density.

The Sega Dreamcast CPU is a two-way superscalar SH-4@200MHz which is a later design of the same architecture which the CEO above is trying to use (patents expiring like the 68k). The SH-4 has larger caches and a smaller die size (wire lengths are shortened and transistors switch faster potentially giving better performance) but the integer performance is still comparable to the older 68060 at the same clock. The SH-4 has a vector/SIMD FPU with single precision support which improves 3D gfx performance. The 68060 has no SIMD/vector FPU and the Apollo core SIMD has no floating point support nor is likely to ever support fp with the ISA and the way the SIMD unit is joined to the integer unit. An SIMD unit supporting single precision fp is the easiest way to significantly improve 3D performance (I wouldn't suggest it in the http://apollo-core.com "Polygon Pushing Performance of the 080" thread or you are likely to be chastised for not being realistic and I wouldn't be surprised if your message was removed). The SH-4 SIMD support is rigid so perhaps it was designed specifically for Sega. One of the Dreamcast evaluation teams looked at the PPC 603e but it didn't have SIMD support to help with gfx. A more energy efficient PowerVR GPU was chosen over a faster 3dfx (Voodoo 2/Banshee performance) GPU which was probably possible because of the SIMD support in the CPU. The Dreamcast has modest performance with "off the shelf" components compared to the later highly customized Playstation 2 which quickly resulted in its demise.