@tomazkid

The only way that would be feasible is by making a cache-controller with three busses:
G5 front side bus, 60x front side bus and memory bus for connecting L3 cache (the G5 doesn't support an L3, which is why you would need to make the support for it yourself). Given a reasonable amount of L3 cache running at the G5 front side bus clock and bus width you would get a reasonable amount of data throughput. It would not come cheap, though.

At some point this might happen for the the G4 Macs, might be something to keep an eye out for.

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This weeks pet peeve:
Using "voltage" instead of "potential", which leads to inventing new words like "amperage" instead of "current" (I, measured in A) or possible "charge" (amperehours, Ah or Coulomb, C). Sometimes I don't even know what people mean.