Seventh article of the series.
The SIMD/vector unit of NEx64T is finally presented, showing how it works with some examples well known in the literature and comparing this new architecture with the better known as well as "renowned" ones, in order to show its advantages, innovations and potential.
English: https://www.appuntidigitali.it/21533/nex64t-7-the-new-simd-vector-unit/
Italian: https://www.appuntidigitali.it/21374/nex64t-7-la-nuova-unita-simd-vettoriale/

@cdimauro

Given the propensity (for intel in particular) to just keep widening the vector unit and throwing more and more instructions at it, how do you intend to remain compatible in the long term?

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Doing stupid things for fun...

@Karlos: the long term is represented by vector length-agnostic ISA extensions, which give the final solution to this problem (delegating to the implementation / microarchitecture those details).

NEx64T supports both vector length-agnostic and fixed-size vector registers with its ISA extensions and already extended the latter with 1024-bit fixed-size vector registers.

Intel has only reached 512 bit in this case, with AVX-512. There's still an encoding free / available in the EVEX prefix (introduced for AVX-512 instructions) which can be used for a hypothetical 1024 bit size.

However I don't know if something like that will happen in future, because having very large registers causes clock skew issues. On top of that, the chip consumes much more power. Both things are the reasons why the processor's clock slows down when using such wider units (it happens with AVX as well).

In short: Intel might introduce AVX-1024, reaching NEx64T.
Beyond 1024 bits is very unlikely for both Intel's x64 and NEx64T, but eventually they require new encodings (since all configurations are used by the 1024 extension).
NEx64T has an option to recycle the MMX encoding for introducing a 2048-bit register registers size, at the expense of not allowing anymore to execute both vector and SIMD instructions at the same time (which also happens with 1024-bit registers size).

However, and as I've stated, vector length-agnostic is / should be the way to go. If Intel engineers are smart enough, they should introduce it using the free encoding which is still available, instead of adding AVX-1024.

@cdimauro

Quote:

which give the final solution to this problem

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Doing stupid things for fun...

@Karlos: I can understand if we're in Germany (where I avoid to use such term), but... everywhere else?!? It's the right way to express the concept!