@alx

Quote:

Imagine that you've been running some audio application that utilises all eight threads, and then want to load another application that needs four of the threads to do something else. At a minimum, it would be good to be informed that the first application is hogging the XMOS chip, and given the option to terminate it. On a more advanced level, perhaps applications could indicate to the OS that they can gracefully fall-back to using less of the XMOS's threads, so the user can choose to throttle the XMOS-hogging application and run another...

This is something that I'd like to know more about also. Will it be truly this integrated into the OS, or will it be more separate? (ie you have to have a Xorro bridge card installed to access the Xena chip, and Xena code is loaded from the CF slot etc)

Would be nice to know more from the devs.

@ChrisH

The communicate with the host's main processor must be interupt driven. Interupts of the host's main cpu that is. Hence I fail to see the benefit to solder the XMOS directly to the mainboard, instead of putting it on a (dma enabled) PCI(e) card (or maybe even hook it up to the usb bus). Communication between XMOS and the host depends on how the host system handles the interrupts.
Anyway, it's an interesting uC (but so are many).

Last edited by Zylesea on 06-Jan-2010 at 02:25 AM.

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Hey - I'm now allowed to post freely and will try to answer questions: I also recommend you head over to our official community if you have questions about the XMOS processor.

http://xcore.com

Just to say up-front, I don't know how the XMOS chip is coupled to the main host CPU, so can't help you out with info there.

Looking forward to seeing how this develops.

@vidarh

Quote:

vidarh wrote: @-pekr- Got this from user "JonathanMay": I can't post on the forum yet (just signed up), but wanted to post the following. Can anyone help? "Hi guys. I'm from XMOS (www.xmos.com). Unsurprisingly, we noticed the activity on these forums... I thought I'd come along and have a read through. First thing to say is that for technical questions about XMOS and the processor architecture - as well as free, open source tools downloads, many many applications examples and documentation, head over to the XMOS website (http://xmos.com) or the XMOS community website (http://xcore.com). Couple of quick answers to the above: no there is currently no OS for the XMOS chips. You can use the parallelism for whatever you want. There are 8 threads per core, and the timing of the execution of the threads - written in high level languages such as C, C++ and XC - is deterministic allowing you to control hardware devices with real-time guarantees. As regards to the "future" being in GPGPU architectures: that's a little tenuous in my opinion.

GpGPU is already here e.g. Matlab, CyberLink applications, Adobe applications, MacOS X 10.6 (OpenCL), Windows Viista**/7(DirectX11(1)'s Compute Shader 4.0/4.1/5.0).

The mainstream fusion CPU+GPU combines the two advanatges i.e. taskbase (threads with out-of-order performance) and data parallelism (e.g. SIMT). Intel Core i7-mobile already has 8 threads.

**With DX11 runtime updates.

Quote:

They are hard to program, do not offer a very general form of parallelism and are somewhat limited to extremely data-parallel operations. They are also very expensive and inflexible. What is interesting about them is that their rise has demonstrated that it really isn't that hard to write parallel programs - even on unconventional, inflexible and constrained architectures with untidy languages. XC is a language developed by XMOS where parallelism is inherent and at the language's core: par { thread1(); thread2(); } What will bring parallelism into the mainstream is a solid programming model and an architecture that efficiently executes this model. This is what XMOS believes it has created. There will always be sceptics: this is why the tools are free and include a cycle-accurate simulator of the architecture: you can write some programs and try them out before you even buy an XMOS device. Welcome on board and best of luck - I'll do my best to answer questions but as I said before, come on over to our forums/website if you want more detailed answers/discussion. Jonathan"

The programming model is similar Intel Larrabee i.e. 4 threads per lite-X86 core with 512bit wide SIMD i.e. 32 lite-X86 cores * 4 = 128 threads.

With NVIDIA CUDA, the threads are organised in a grid. Each thread has a thread id, which can be used to compute memory address and make control decisions. It’s not hard to do when you are crunching numbers.

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@Hammer

That's exactly my feeling wrt Xena... its usefulness is going to be directly related to how well it's integrated with the rest of the computer. If it's only connected to the PCIe bus, even if it's a busmaster, any PCIe graphics card will easily blow it out of the water (when's the last time you saw a card with only 8 shaders?). On the other hand, if Xena has access to things like the audio pipeline then interesting things become possible that CUDA just can't do.

programming model isn't similar to LRB. With LRB you can pass threads to and from the processor, you wont be able to with Xena because it's alien. It's just some gimped processor on a bus with 64kb sram. What a friggin joke. It's not even "amiga like".

Last edited by koft on 06-Jan-2010 at 07:52 AM.

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@koft

Quote:

koft wrote: programming model isn't similar to LRB. With LRB you can pass threads to and from the processor, you wont be able to with Xena because it's alien. It's just some gimped processor on a bus with 64kb sram. What a friggin joke. It's not even "amiga like".

Exactly what is not "Amiga like" about having co-processors? Remember the copper? Remember the PC bridge cards? Heck, remember the Amiga keyboard? (it had an embedded 6502 compatible chip on it) For that matter, the SCSI card I used to have for my A2000 had a Z80 on it.

Amiga has a long history of using relatively simple, low powered co-processors to offload the main CPU for specific tasks with great effect - it's the *only* reason Amiga managed to stay competitive long after PC's had gotten far more raw CPU power.

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@koft
Do I smell sour grapes here? otherwise why such a harsh comment?

What you say about "how Xena Works" is pure speculation.
This thing is complex and even people that deisgn chips for a living needs to deeply investigate the matter.
We are indeed asking how it communicates with the rest of the system and many have "proposed" different theories, do you happen to know insider informations we don't have?

As for Hammer comments we should consider that:

1)Specs are subject to change and they said there will be different configurations available (so we can assume that one will mount the XcoreG4 instead of the G1)

2)that chip is there to create software that takes advantage of it and then scale it on a cluster of Xcores connected to a Xorro card or even several Xorro cards interconnected. I hear these chips are extremely cheap and we got fantastic scalability there.

3)IF top engineers that were making Transputers when you were very young think the Xcore has huge potential even against GP-GPU you should further investigate the matter instead of counter comment with old or incomplete knowledge (on this technology at least).

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xcore is interesting addition.
I assume it's connected to southbridge's PCI via xilinx ship.
xore can deliver nice performance for very small power usage. But it's not a general purpose CPU accelerator. It is not meant to be (even though it could deliver 102000MIPS).
On xcore pages (and from industry) one can see interesting use for the xcore.
It has got world wide attention already.

Last edited by KimmoK on 06-Jan-2010 at 10:30 AM.

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@DAX
Quote:

We are indeed asking how it communicates with the rest of the system

You're right. Actually, this is THE crucial point which will decide whether Xena is a genius idea or a bad joke, and it's not really discussed on the A-Eon website.

For what we know, Xena's I/O lines are routed to the Xorro port. I hope there is more than that!

We're all (including A-Eon) talking about the Classic Amiga's custom chips, but Jay Miner and his team didn't think :
"Ooooh, crap, we'll just put those chips somewhere on the board, give them some kind of vague connectivity, and programmers will do what they want with them. I, for one, don't have a clue about what they might be useful for."

So the question is (Rogue, TrevorD, if you're reading this...)
Does Xena have priviledged access to memory? DMA? Can it directly access the peripherals using the southbridge? Can it send interrupts to the CPU?

In a single, somewhat provocative question :

What can Xena do that a XMOS chip embedded on a PCI-e card couldn't?

@Lynx

Quote:

Lynx wrote: In a single, somewhat provocative question : What can Xena do that a XMOS chip embedded on a PCI-e card couldn't?

Simple.. Be guaranteed to be on everyone's X1000 system. If it was an add-on option it would have a lot less use

And of course possibly have direct CPU access

Last edited by BinoX on 06-Jan-2010 at 10:32 AM.

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@KimmoK
Quote:

On xcore pages (and from industry) one can see interesting use for the xcore.

No! The Best uses are missing! The ones the Amiga Community will create!

Go check the inMos T800 Transputer chip, it was far less of a general purpose CPU accelerator and yet it was used exactly as that (transputer boxes to accelerate 3D rendering with a software called DGS).

Thus I don't think the only usage is for HW emulation (ie:Consoles, Sid etc.) or industrial controllers...(Amigans will show them).

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@Hans, @Thread

Does anyone know if it's possible to run Java on llvm? Wouldn't that help in getting Java to Amiga?

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@MrFancyPants

I think xcore could function as a JAVA accelerator etc. but it's easier to be implemented in SW on the CPU.

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@thread

I have to say that I for one am very excited / interested in this XCore chip. I have for a long time wanted to merge my Electronics projects with my Amiga stuff in such a manner that I can create useful things for AmigaOS. I had been toying with the idea of going into driver development (since I am used to dealing with things at a hardware level), and the XCore gives me a lot more scope in that respect.

Applehammer

@JonathanMay

Welcome!

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@BinoX

Quote:

Simple.. Be guaranteed to be on everyone's X1000 system. If it was an add-on option it would have a lot less use And of course possibly have direct CPU access

"Possibly"...I hope so! For what we know, it could very well be *only* accessible by external hardware via the Xorro port! Actually I don't think so, now THAT would be stupid. Mmmhhh...it would in some cases allow for cheaper expansion boards because some of the computing power would be on the motherboard (for the boards that would need a XMOS chip and would otherwise embed their own)? Well, about 10¤ cheaper (the alledged price of a single-core XMOS chip)...that's not much given the presumably high price of X1000...

Now if we have direct CPU/memory/peripherals access, that would be another story.
Moreover, XMOS systems are very scalable, each process can easily communicate with another on ANY connected XMOS chip. That would mean a Xorro-connected multi-XMOS chips board would easily access all resources connected to Xena. That would be great!
But...it's still only a hope. I wanna know more!

@Apple_hammer
And rest assured the community here will appreaciate your work in case you will decide to do it

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fyi some examples: http://www.youtube.com/group/XMOSprocessor

(btw does x1000 have legs?)

Last edited by KimmoK on 06-Jan-2010 at 12:21 PM.

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@CodeSmith

Quote:

CodeSmith wrote: @Hammer That's exactly my feeling wrt Xena... its usefulness is going to be directly related to how well it's integrated with the rest of the computer. If it's only connected to the PCIe bus, even if it's a busmaster, any PCIe graphics card will easily blow it out of the water (when's the last time you saw a card with only 8 shaders?). (SNIP)

Geforce 9100M G has 8 CUDA/SP cores.

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