@NutsAboutAmiga

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NutsAboutAmiga wrote: @wawa Well FPGA plus a real CPU will probably get the time right every time, while a emulated CPU can depend on how complicated an instruction is to emulate, one game might run well or even better than the real thing, another game might not run as expected, but often there is latency what you see on screen is not what is happening, so you react too late to things happening on the screen.

Exactly... real CPU always have an edge against emulated ones and it's specifically due to the fact that the emulated one is not real hence not 100% reliable.

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@wawa

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wawa wrote: @cdimauro Quote: I don't know what are the numbers on the Amiga community. Certainly thousands of users can be a good number, but the idea that I made frequenting the Amiga community is that there can 4-5 thousands of passionate amigans around, but not only of them will buy a NeoAmiga platform looking at the interest in fpgaarcade which still has not been widely delivered you can sense the actual interest, i guess.

Have you some numbers?

@NutsAboutAmiga

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NutsAboutAmiga wrote: @cdimauro My idea is different it's less costly as you do not need the USB, HDMI and SDCARDS, as you have it connected to host system. During emulation the FPGA is used as custom chips for computer your emulating, but when not emulating the FPGA can be reconfigured to be used to encode or decode video or audio.

OK, I got it now. I don't see it as a viable solution.

You've to connect the FPGA card to the host system, and it means that you must use something like USB or PCI-Express (I don't consider the PCI because it's too much old and limited). It means that the communication between the CPU and the FPGA will have a long latency, which kills the performance of the whole system. Especially because you need to sync them, and it takes too much time. And the more accurate is the emulation, the more sync problems will be.
So, no: it doesn't work.

It doesn't even make sense, because today even a low-end computer is able to fully emulate an Amiga at a good speed, as wawa stated.

@asymetrix

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asymetrix wrote: @cdimauro Whos project is TiNA ?

You can look at the owner of the registered site.

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can he/she confirm the project is Cancelled if at all.

He's the owner: who else can?

@NutsAboutAmiga

Quote:

NutsAboutAmiga wrote: @wawa Well FPGA plus a real CPU will probably get the time right every time, while a emulated CPU can depend on how complicated an instruction is to emulate, one game might run well or even better than the real thing, another game might not run as expected, but often there is latency what you see on screen is not what is happening, so you react too late to things happening on the screen.

A CPU can be emulated as accurate as possible: it depends entirely on the documentation and effort on the emulation.

There are entire platforms that are already fully cycle-exact emulated (simulated, in this case).

An emulated CPU is preferable IMO, because you can change it on the fly, depending on the configuration that you want to emulate (or simulate, for a cycle-exact model), or upgrade / fix. The same is for the chipset.

Anyway, I think that an emulator doesn't have to emulate perfectly everything. In the Amiga case, the requirements and features are well defined in the well known Hardware Manual. It means that, for example, there's absolutely NO need to emulate the complete Blitter diagram state, because it's clearly stated in the manual that it's just a representation of the current implementation, that in the future can change, and that coders do NOT have to take it as a reference.

In short words, who cares if there's some badly written application/game that doesn't work in a "synthesized" system. For these, the solution is WHDload...

@cdimauro

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Have you some numbers?

nah. but look at the thread on aorg, pretty much everyone is interested, whether he has any other amiga ng bias or not. also majsta said he wahs overwhelmed by demand and outsourced the manufacturing to someone else, ahich i dont have a reason not to trust in as it seems everything he said till now was truth.

I haven't said that, I don't have reasons to don't trust you. But I just asked for some number to get an idea of the possible market. That's all.

Last edited by cdimauro on 06-Nov-2013 at 06:26 AM.

Well I am not in the least bit surprised. Why does everyone say WE will build the super amiga.
Pragamtic, sensible, planned and ONLY one leader!

Start small and develop something that can be built on for the future.

Natami was a joke and Tina looked like vapourware. The website looked silly, frankly.

There is now talk of a chipset being developed at amigacoding.de. No idea if anything will come of it but hopefully a pragmatic approach can be found.

@cdimauro

I don't get it. How does PCIe have a longer latency than an m68k local bus? You get 32 bits address or 32 bits data every 16 nanoseconds, and that's just a x1 PCIe 1.1 link. A fairly cheap Spartan6 can do the PCIe end point AND the DDR controller in hardware, so it's not even a lot of hassle these days.

Btw, most Amiga CPUs are not cycle-exact 68000 anyway

Edit: I had mistakenly written micro instead of nano. No wonder cdimauro got confused.

Last edited by olegil on 17-Dec-2013 at 09:37 AM.

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Using "voltage" instead of "potential", which leads to inventing new words like "amperage" instead of "current" (I, measured in A) or possible "charge" (amperehours, Ah or Coulomb, C). Sometimes I don't even know what people mean.

Quote:

adrianbrowne wrote: Well I am not in the least bit surprised. Why does everyone say WE will build the super amiga. Pragamtic, sensible, planned and ONLY one leader! Start small and develop something that can be built on for the future.

Even developing with little steps cannot be possible without people doing the little steps.

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Natami was a joke and Tina looked like vapourware. The website looked silly, frankly. There is now talk of a chipset being developed at amigacoding.de. No idea if anything will come of it but hopefully a pragmatic approach can be found.

At least there's something which is working on it.

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olegil wrote: @cdimauro I don't get it. How does PCIe have a longer latency than an m68k local bus? You get 32 bits address or 32 bits data every 16 microseconds, and that's just a x1 PCIe 1.1 link.

16us are an eternity. It means that you can submit roughly 60K data requests per second, which is just able to cover the needs of 2 Paula audio channels.

The Amiga chipset issues up to 3,5Mtransactions (1 transaction = 16, 32, or 64 bit) per second...
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A fairly cheap Spartan6 can do the PCIe end point AND the DDR controller in hardware, so it's not even a lot of hassle these days.

See above: you can only count on the DDR.
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Btw, most Amiga CPUs are not cycle-exact 68000 anyway

Yes, I know it, but if you want full compatibility you need to be cycle-exact. An FPGA can provide compatibility with all CPUs, because you can change the "firmware" from one execution / boot to another. And you can update the firmware to be more, and more accurate.

@cdimauro

Obviously I meant nanoseconds. With PCIe 1.1 you get 62.5MT/s, which is a LOT more than 3.5MT/s.

_________________
This weeks pet peeve:
Using "voltage" instead of "potential", which leads to inventing new words like "amperage" instead of "current" (I, measured in A) or possible "charge" (amperehours, Ah or Coulomb, C). Sometimes I don't even know what people mean.

@olegil

http://www.knjn.com/ShopBoards_PCI.html

I found a PCIe mounted FPGA's, but they are expensive.



I can complicity understand that many projects are based on Raspberry PI and Andrino for more simple things.

Last edited by NutsAboutAmiga on 17-Dec-2013 at 12:28 PM.
Last edited by NutsAboutAmiga on 17-Dec-2013 at 12:27 PM.

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@cdimauro

Quote:

16us are an eternity. It means that you can submit roughly 60K data requests per second, which is just able to cover the needs of 2 Paula audio channels.

but what if you have AUX header connector you can connect to your sound card internally, the Paula chip is simple chip, what it does is play back a memory buffer you give it, at the frequence you set.

I can probably go step longer and make 16bit, 32 channel Super Paula in FPGA, just for fun, instead of 8bit, 4 channels in the Amiga500

AmigaOS4 applications might use it for a lot of things, it does not need to be just for emulating stuff, the FPGA is reconfigurable.

Last edited by NutsAboutAmiga on 17-Dec-2013 at 12:44 PM.
Last edited by NutsAboutAmiga on 17-Dec-2013 at 12:18 PM.
Last edited by NutsAboutAmiga on 17-Dec-2013 at 12:17 PM.

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@NutsAboutAmiga

Xilinx Virtex-5 XC5VLX20T is a pretty big chip.

The smallest Spartan-6 with PCIe is MUCH, MUCH cheaper.

Comparison:
http://www.digikey.com/product-search/en?mpart=XC6SLX25T-2CSG324I&vendor=122

http://www.digikey.com/product-detail/en/XC5VLX20T-1FFG323C/XC5VLX20T-1FFG323C-ND/1957145

And that's 1 of the cheapest vs 84 of the most expensive. Buying 84 of the cheapest will give you about half that price again.

_________________
This weeks pet peeve:
Using "voltage" instead of "potential", which leads to inventing new words like "amperage" instead of "current" (I, measured in A) or possible "charge" (amperehours, Ah or Coulomb, C). Sometimes I don't even know what people mean.

@olegil

Quote:

olegil wrote: @cdimauro Obviously I meant nanoseconds. With PCIe 1.1 you get 62.5MT/s, which is a LOT more than 3.5MT/s.

This is only a theoretical value: it completely misses the packet transmission overhead, and not even consider the latency.

Take a look at this: http://www.fpga4fun.com/PCI-Express4.html
For a 32-bit write (which is the minimum) you need 4 double words (DW, 32-bit) to be transmitted. So, it means that if you transmit only 32-bit data you can get a maximum of 15.63MT/s.
Reading is worse, because you need to transmit one packet for the request (3 DW) and receive another one (4 DW) to get the data. Again, communicating only 32-bit at the time, you can get a maximum of 8,93MT/s.

All this is only for the Transaction Layer. Take a look a this: http://hardwareverification.weebly.com/pci---express-architecture.html

And, again, we are not considering the latency. I have no idea about how much it takes, but from the latter link you can see how long is the round-trip for a packet which is sent through the PCI-Express.

Another thing which needs to be handled is the 16-bit nature of the Amiga chipset. So you have to resort to some trick to signal that you want to send or receive just the 16 higher or lower bits of a (virtual) 32-bit location. While MAY be safe reading 32-bit at the time from the chipset, it's certainly NOT safe to do the same trick for a write.

In the end, I really doubt that it can be a useful way to follow.

Anyway, why don't let the FPGA to do also the CPU simulation? FPGAs nowadays are cheap and have a lot of resources. Why using them to do only half of the work? It doesn't make sense, for me. It's better to simulate an entire Amiga machine.

@NutsAboutAmiga

Quote:

NutsAboutAmiga wrote: @cdimauro Quote: 16us are an eternity. It means that you can submit roughly 60K data requests per second, which is just able to cover the needs of 2 Paula audio channels. but what if you have AUX header connector you can connect to your sound card internally, the Paula chip is simple chip, what it does is play back a memory buffer you give it, at the frequence you set. I can probably go step longer and make 16bit, 32 channel Super Paula in FPGA, just for fun, instead of 8bit, 4 channels in the Amiga500

You need to completely emulate Paula if you want to gain the compatibility.

I also found impractical to connect stuff internally on the motherboard. I prefer out-of-the box products...
Quote:

AmigaOS4 applications might use it for a lot of things, it does not need to be just for emulating stuff, the FPGA is reconfigurable.

Why you are talking about OS4 application now? I don't think that they will make use of something like Paula, because AHI is a better and widely adopted standard for more modern applications.

Finally, OS4 machines should be capable to emulate well at least an OCS/ECS Amiga machine.