@ppcamiga1

Quote:

ppcamiga1 wrote: @matthey Quote: It doesn't help that NG AmigaOS businesses have ignored and practically blocked 68k AmigaOS FPGA development that has a better chance to be NG than PPC PC hardware. This is BS. I like my vampire but it is still many times slower than any ppc.

Try the DevilutionX benchmark.

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@Hammer

Quote:

This is BS. I like my vampire but it is still many times slower than any ppc.

Quote:

Try the DevilutionX benchmark.

I think it does depend on the task.

The APOLLO 68080 CPU is clock by clock generally more performant than most PowerPC CPUs.
We explained that PowerPC often needs more instructions for doing the same job.
This can be 3 PowerPC instructions for doing what a single 68K instruction does.
But sometimes it can also be 4/5/6/ or 7 PowerPC instructions for doing what a single 68K instruction does.

Of course the FPGA does limit the clockrate.
While you get 100MHz in the FPGA putting the same core in an ASIC might give you 1 Gigaherz.

If you compare Vampire and PowerPC systems
then Apollo 68080 has better performance per clock
But PowerPC Systems have higher clock - as they use an ASIC.

If you look not only at the CPU clock but also at the memory performance
than the Apollo 68080 does in fact beat many PowerPC systems.

The memory performance of many PowerPC systems is pretty bad
and the Data-Cache if many PowerPC system can not automatically prefetch.
The G5 PowerPC 970 can - and the Apollo 68080 can both do this.
And this gives both a major performance boost.


If you look at some applications or games like Diablo port
then you can see that Diablo runs on the Vampire a lot smoother
and faster than on AmigaOne with 1000 MHz PowerPC.
The reason is for a big part the better Data-Cache of the Apollo CPU and its better memory performance.

@OneTimer1

Quote:

OneTimer1 wrote: @cdimauro Quote: cdimauro wrote: Again, Red Herring. You're trying again to change the topic. The topic is "32-bit PPC on FPGA" but people stopped writing about it, after it was explained why a slow PPC is a bad idea.

Why you're again trying to change this part of the discussion? YOU talked about the Amiga OS and YOU made PRECISE statements about it, which were FALSE.

Why couldn't you be intellectually honest to admit it, instead of trying to change the topic?


@matthey

Quote:

matthey wrote: cdimauro Quote: So, there's no real opportunity 'til now. And you can't expect any source code opening, after so long: it's clear evidente that they want to keep closed their goose that laid the golden eggs. However, you were also in touch with Jens: you can contact him to see if there's some space for a different project. The Natami project led by Thomas Hirsch was very open and transparent with a clear goal to revive the 68k Amiga. http://obligement.free.fr/articles_traduction/itwmichalakakos_en.php Quote: Thomas Hirsch, the creator, wanted to revive the Amiga long ago. He worked for many years rebuilding the OCS and AGA chipsets. Gunnar von Boehn and Peter Kaltstein were working on their daily jobs in the same department of a hardware development lab as Thomas. They teamed up with Thomas to help him to get the NatAmi out, and were very motivated by seeing the 1st prototype in action at an Amiga-meeting in 2008. Soon after, more people joined the team. The original prototype was designed like an A4000 using 50MHz memory. But starting in 2008, Thomas has been redesigning the Amiga DMA engines to make full use of modern memory. This means that memory bandwidth is greatly enhanced. Jens had a similar philosophy as Thomas and tried to open the N68050 CPU core created for the Natami project. Is there any question where the closed hardware secretive cult philosophy came from? The Natami project was too hard lacking a high performance 68k CPU core and being blocked by AmigaNOne IP squatters. While AmigaNOne hardware was selling in the low thousands, the open and transparent Natami project generated huge interest without advertising. The Natami "MX Bringup Thread" had 761,487 views at one point and likely went significantly higher. Natami "MX Bringup Thread" Quote: [...] The more open and transparent Natami project felt to me like it generated more excitement than the AC/Vamp project. I posted the Natami "MX Bringup Thread" views to various Amiga forums claiming this was an indication of a large 68k Amiga retro market but it was largely discounted. It wasn't until later that THEA500 Mini success backed up my claims and suggested that there may be a large enough market for mass production and creating competitive affordable hardware. I would have also liked to see a professionally developed "revived" retro 68k Amiga but some things are too hard in Amiga Neverland.

That was a big missing opportunity for the Amiga revival which I think that it's very difficult, if not even impossible, to be again.

That's because the THEA500 Mini project has already took the chance to "revival" the platform for plenty of people which used our beloved platform and bought it to revive the good old times.

Now you can't do the same again, because people will not buy a duplicated of what they've already bought.

That's why also the A600GS project has no chances to succeed: time over. It will sell, for sure, because there are passionate which like to have better platforms compared to what the THEA500 Mini offers, but the average guy which has already bought the latter will not buy the new one.

@Gunnar

Quote:

Gunnar wrote: The APOLLO 68080 looks like this. 1) Icache can fetch 16 BYTE per cycle. These 16 BYTE can span 2 cache rows. This means the 68080 does NOT need to align loop in memory to have full speed. The 68080 is the first 68k CPU with this feature. In parallel to providing instructions to the Decoders the APOLLO 68080 Icache reload more instructions from memory to Icache. This is a feature greatly increasing performance. 2) The Decoders can decode up to 4 instructions per cycle. But frankly 4 instruction in parallel per cycle is an uncommon case. Normally code runs around 2 instructions per clock. 3) the Apollo 68080 has TWO EA units. Each EA unit can calculate address of using memory (read/write) and can execute instructions like LEA, ADDA, SUBA on its own. 4) The DCache can load 8 BYTE of DATA each cycle to the CPU. The 8 Byte can be of any memory alignment and they can span even 2 Cache lines. This feature is exceptionally and gives the 68080 great performance in memory operations. In parallel to doing one READ the DCache can even accept one WRITE to it per cycle and it can in parallel Reload and Prefetch Data from Memory. The Apollo 68080 DataCache will watch memory access and can by itself detect streaming access like memory copies, on detecting such access pattern the DATA Cache will do automatically prefetch memory load. This feature is great. It gives the CPU a huge memory performance. The IBM 970 PowerPC was the first PPC having the same feature as the APOLLO 68080 All previous PPC can not do this automatic memory prefetching and have because of this a much lower memory performance. This feature makes a bug difference and is the reason why Apollo 68080 at 90MHz can outrun in memory operations a Motorola G4 PPC at 1000MHz running in an AmigaONE. 5) The APOLLO 68080 has 4 ALU Units: - 64bit AMMX SIMD unit - FPU - 2 normal integer ALUs

AC68080's quad 68K decoders with two ALU/AGU + FPU reminds me of AMD K5 (1996)'s quad X86 decoders with two ALU/AGU + FPU.

For comparison, besides the P5 Pentium uArch,
AMD K5 (1996)
Port 0: ALU
Port 1: ALU
Port 2: FPU i.e. FP ADD, FP MUL, FP DIV,
Port 3: Branch
Port 4: Splits into AGU/Load Store, AGU/Load Store


AMD K6 MMX (1997) has two short X86 decoders + one long X86 decoder + one microcode decoder backed by two ALU/AGU + FPU.

Port 0: INT ALU, INT MUL, INT DIV, MMX ALU,
Port 1: INT ALU, MMX ALU,
Port 2: FP ADD, FP MUL, FP DIV,
Port 3: AGU, Load Data
Port 4: AGU, Store Data
Port 5: Branch

Port 0 and 1: MMX Shift, MMX MUL
Feed by 16 bytes per cycle from L1 instruction cache. Reorder buffer (ROB) has 24 entries with 48 integer registers and 21 MMX/FP registers.

AMD K6-II 3DNow (1998)
Port 0 and 1: MMX Shift, MMX MUL, 3DNow MUL, 3DNow ALU

Quake uses both integer and floating point.

AMD wouldn't be splitting FPU port's FMUL and FADD units until K7 Athlon.

Quote:

6) 2 parallel working Bus Memory Controller The 68080 has 2 independing memory controllers. The fastmem memory controller supports 64Bit access and support prefetching and bursting. The 64bit wide memory bus allows the 68080 to reach far better memory performance than any 68K before. The Apollo 68080 has in addition a second 32bit memory controller which can in parallel operate.

68060's 68040 32bit bus was kept separate from 88000/Moto PPC 601's 64bit 60x bus.


Quote:

Both controllers can work in parallel without blocking. The Amiga bus/ Zorro and Chipmemory are connected to the 2nd controller. This allows the 68080 CPU in an Amiga to e.g. do for example in parallel a write to chipmemory, while at same time loading more instructions from fastmemory. The power of two independent memory controllers makes the 68080 extremely powerful in Amigas. As you will know the Amiga 1000/500/600/2000 mainboards speak 68000 protocol, while the A1200,A3000,A4000 mainboards speak the differen 68020/30 protocol. The Motorola 040/060 CPU have another incompatible protocol This makes using 040 or 060 CPU complicated in Amiga - as you need extra logic to translate the protocols. This makes 040 and 060 slower in accessing Amigas chipmemory. The APOLLO 68080 CPU speaks natively both 68000 and 68030 bus protocol. Thus means you can directly connect it to Amiga mainboards - and not need any translation that would slow down.

Dave Haynie's Acutiator chipset would have supported 68040 class CPU but this was rejected around the end of 1991. Amiga's next gen R&D project was focused on PA-RISC.

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@Gunnar

Quote:

I think it does depend on the task. The APOLLO 68080 CPU is clock by clock generally more performant than most PowerPC CPUs. We explained that PowerPC often needs more instructions for doing the same job. This can be 3 PowerPC instructions for doing what a single 68K instruction does. But sometimes it can also be 4/5/6/ or 7 PowerPC instructions for doing what a single 68K instruction does. Of course the FPGA does limit the clockrate. While you get 100MHz in the FPGA putting the same core in an ASIC might give you 1 Gigaherz. If you compare Vampire and PowerPC systems then Apollo 68080 has better performance per clock But PowerPC Systems have higher clock - as they use an ASIC. If you look not only at the CPU clock but also at the memory performance than the Apollo 68080 does in fact beat many PowerPC systems. The memory performance of many PowerPC systems is pretty bad and the Data-Cache if many PowerPC system can not automatically prefetch. The G5 PowerPC 970 can - and the Apollo 68080 can both do this. And this gives both a major performance boost. If you look at some applications or games like Diablo port then you can see that Diablo runs on the Vampire a lot smoother and faster than on AmigaOne with 1000 MHz PowerPC. The reason is for a big part the better Data-Cache of the Apollo CPU and its better memory performance.

AmigaOne SE/XE's Northbridge is sub-standard.

https://www.youtube.com/shorts/oK2U_xoTWHM
Diablo on Pentium 100Mhz (66Mhz 64bit FSB, PCI graphics card).

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@Hammer

You must be bored if you're dredging this thread up.

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@Hammer

"AmigaOne SE/XE's Northbridge is sub-standard."

I wonder maybe a fast FPGA, might be able to replace that old and slow Northbridge
perhaps not the biggest market for a thing like that and expect the "software" workaround needs to remove as well.

It should be possible to get as fast as the Pegasus II, I think maybe a bit faster.
I love some newer DDR5 memory too, maybe we can speed up some DMA copy stuff?

Last edited by NutsAboutAmiga on 03-Mar-2025 at 05:09 PM.
Last edited by NutsAboutAmiga on 03-Mar-2025 at 05:08 PM.

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@NutsAboutAmiga

Quote:

NutsAboutAmiga wrote: I wonder maybe a fast FPGA, might be able to replace that old and slow Northbridge perhaps not the biggest market for a thing like that and expect the "software" workaround needs to remove as well.

In theory yes, in reality....

The April chips kinda tried to fix some issues from the outside and even with very little logic they ended up being expensive in order to run at the needed speeds.

A NB is complex and needs to have low latency even as an ASIC and now you want to get to an even lower latency (to make use of faster RAM) on a FPGA?
The ones used in Vampires might have enough logic cells, but I doubt you'd get to up speeds on par with the Artcia let alone beyond it.

Would cost about as much as SAM460 and be harder then to get Moana up to snuff (WITHOUT any sources ).

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@NutsAboutAmiga
Memory controllers have been integrated on MPUs and SoCs for about 20 years now because integration offers better performance and lower communications latency. SoCs are a further integration of I/O with CPU and GPU cores. Integration is what allowed Jay Miner to bring an affordable 68k Amiga to market and what Commodore failed to continue doing with the 68k Amiga resulting in their bankruptcy. Commodore planned for a 68k Amiga SoC but failed to deliver the Commodore estimated $100 USD per unit cost savings that would have saved them. Integration is what allows emulation to outperform 68k and PPC cores with low end ARM SoCs. The history of the Amiga is a lesson in integration. Jay Miner foresaw it but could not save the Amiga from oblivious financiers like Irving Gould and Trevor Dickinson. For example, Trevor does not believe it is necessary to integrate a standard FPU in AmigaNOne "desktop" hardware with a price several times that of the competition. Trevor and his Amiga wannabe hardware are repeating the Commodore 1990s failures all over again.

Last edited by matthey on 03-Mar-2025 at 09:53 PM.
Last edited by matthey on 03-Mar-2025 at 09:39 PM.

@Karlos

A FPGA will always be slower and more expensive than a CPU produced with similar processes.

Unless your CPU is out of production (68k) or you need some special add ones, you would not use an FPGA with Softcore as a replacement for a real CPU.

---

When it comes to a RISC CPU it's speed is depended of high clock cycles and built in caches, nothing what an FPGA could do better.

You have mentioned the reduced complexity of a RISC CPU, the resources freed by the simplified Core are used for more registers and a complex FPU, the internal FPU of a PPC might use more transistors than the core itself.

And squeezing the PPC into an FPGA will solve nothing, AFAIK there are still PPC CPUs available that run circles around a FPGA with a soft-core, but the real expensive part is the design for the main board.

Last edited by OneTimer1 on 03-Mar-2025 at 11:14 PM.

@matthey

Quote:

Trevor does not believe it is necessary to integrate a standard FPU in AmigaNOne "desktop" hardware with a price several times that of the competition. Trevor and his Amiga wannabe hardware are repeating the Commodore 1990s failures all over again.

Trever is a investor, not someone with the technical background, sadly. But most AmigaONE has normal FPU, and even one without one, does have good performance, but it’s a mounted of work to support SPE instead, it doesn't make life easier for anyone.

Thankfully there is a few dedicated developers willing to update their stuff. Even if I do not think it’s good use of their time, it’s their time to waste. What this means for the users of A1222 I don’t know. But perhaps not everything is going to suck.

The new clib having a shared amiga library backed, allows the clib to optimized for different PowerPC ISA’s that’s at least a good thing, and should help. A normally static compiled binary is a lot larger and does not have that advantage.

Last edited by NutsAboutAmiga on 03-Mar-2025 at 11:24 PM.
Last edited by NutsAboutAmiga on 03-Mar-2025 at 11:22 PM.
Last edited by NutsAboutAmiga on 03-Mar-2025 at 11:22 PM.

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@Kronos

https://www.raypcb.com/fpga-processor/

Intel Stratix 10 GX 2800

Among the Stratix 10 family, the GX 2800 offers the maximum transceiver count and bandwidth. Key specs:

112G transceivers for dense 4T4R configurations
8752K adaptive logic modules (ALMs)
5818Kb of Hyper-RAM
Fast DDR4 multi-bank memory interfaces

The Stratix 10 GX 2800 retails for $59,465 per unit at the high end. Lower density options with fewer transceivers and ALMs are priced from $18k to $30k.

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@NutsAboutAmiga

Quote:

NutsAboutAmiga wrote: @matthey Trever is a investor, not someone with the technical background, sadly.

Very sadly. Which opened him up to bad technical advice, from people looking to further their own agenda.

Not very sadly for him. Every investor should follow the 1st rule of investing: Never invest money you're not OK with losing. So I hope he enjoys his A-EON X5000/40 with a paltry PPC software library. It only cost him $500k.

Very sadly for us, because his misguided efforts did not do anything to eliminate the divide in the Amiga community, it took up way too much of the limited oxygen in the proverbial room, and after 15 years we have little to show for it.

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@agami

Genius compared to using high end FPGA’s that’s for sure. Any FPGA close to the performance of PowerPC is 10 x more expensive. It doesn't help daydreaming. Of ASIC 680x0 or high-performance FPGA’s.

it did long time for ARM to catch up, and really think this political license issue, in any case pick low-cost chip at EOL, to save a few bucks, and then having to redesign the hardware is not a good idea, the problem in this community is lack of developers, and users, it’s not really commercially viable anymore. As I have written so many times, AmigaOS/AROS/MorphOS does not solve any real-world problems, its obsolete technology, that’s trying to catch up.

Last edited by NutsAboutAmiga on 04-Mar-2025 at 08:31 PM.
Last edited by NutsAboutAmiga on 04-Mar-2025 at 07:49 PM.
Last edited by NutsAboutAmiga on 04-Mar-2025 at 05:08 PM.

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OneTimer1 Quote:

When it comes to a RISC CPU it's speed is depended of high clock cycles and built in caches, nothing what an FPGA could do better. You have mentioned the reduced complexity of a RISC CPU, the resources freed by the simplified Core are used for more registers and a complex FPU, the internal FPU of a PPC might use more transistors than the core itself.

Back in the late 1980s and early 1990s with simplified reduced instruction set computer (RISC) ISAs, "the reduced complexity of a RISC CPU" allowed the RISC transistor savings to be applied to pipelining and caches where larger CISC ISAs and CPUs had difficulty fitting with the early chip transistor budgets.

Complex Instruction Set Computer minimum number of instructions
68000 56 (https://en.wikipedia.org/wiki/Motorola_68000#Instruction_set)
80286 357
x86 1503
x86-64 2034 (https://stefanheule.com/blog/how-many-x86-64-instructions-are-there-anyway/)

Reduced Instruction Set Computer minimum number of instructions
ARMv1 45 (https://arstechnica.com/gadgets/2022/09/a-history-of-arm-part-1-building-the-first-chip/)
PPC 229
RISC-V 47 (https://semiengineering.com/a-minimal-risc-v/)
AArch32v8 526
AArch64v8 575

Today, fitting deep pipelines and caches on a single die are no problem with the problem becoming keeping caches small and close to the CPU cores for reduced latency, where RISC cores with poor code density have a disadvantage. PPC was already not very "reduced instruction set" compared to RISC architectures like ARM and MIPS and later RISC-V. Some of the huge difference is what instructions are made standard with PPC including FPU instructions as standard while AArch64, x86 and x86-64 include FPU and SIMD instructions as standard. Most ARMv8 cores were supporting the original ARM ISA (which grew from the 45 instructions), Thumb ISA, Thumb-2 ISA and AArch64 ISA for over 1000 instructions supported. FPUs require more pipeline stages than integer CPU pipeline stages which uses more transistors. I expect a RISC-V fully pipelined FPU to use more transistors than a scalar RISC-V CPU core without a FPU. PPC CPU cores have more and more complex integer instructions and most are superscalar OoO cores though.

NutsAboutAmiga Quote:

Trever is a investor, not someone with the technical background, sadly. But most AmigaONE has normal FPU, and even one without one, does have good performance, but it’s a mounted of work to support SPE instead, it doesn't make life easier for anyone.

Existing PPC programs that use the "standard" PPC FPU do not have good performance. You would think Trevor would have learned the importance of compatibility when he dropped the 68k and Amiga chipset resulting in only a few thousand PPC systems sold but then he drops the "standard" PPC FPU ruining PPC compatibility as well.

NutsAboutAmiga Quote:

Thankfully there is a few dedicated developers willing to update their stuff. Even if I do not think it’s good use of their time, it’s their time to waste. What this means for the users of A1222 I don’t know. But perhaps not everything is going to suck.

More developer wasted efforts. Only Amiga makes it possible.

NutsAboutAmiga Quote:

https://www.raypcb.com/fpga-processor/ Intel Stratix 10 GX 2800 Among the Stratix 10 family, the GX 2800 offers the maximum transceiver count and bandwidth. Key specs: 112G transceivers for dense 4T4R configurations 8752K adaptive logic modules (ALMs) 5818Kb of Hyper-RAM Fast DDR4 multi-bank memory interfaces The Stratix 10 GX 2800 retails for $59,465 per unit at the high end. Lower density options with fewer transceivers and ALMs are priced from $18k to $30k.

Is that a high end FPGA using a 7nm process that costs as much as a nice car and maybe gives a 500MHz CPU while an ASIC using 7nm would cost less than a bicycle when mass produced and would clock to 2+ GHz using auto layout design tools?

agami Quote:

Very sadly. Which opened him up to bad technical advice, from people looking to further their own agenda. Not very sadly for him. Every investor should follow the 1st rule of investing: Never invest money you're not OK with losing. So I hope he enjoys his A-EON X5000/40 with a paltry PPC software library. It only cost him $500k. Very sadly for us, because his misguided efforts did not do anything to eliminate the divide in the Amiga community, it took up way too much of the limited oxygen in the proverbial room, and after 15 years we have little to show for it.

Trevor has spent more than "$500k" for his X5000 hobby. A-Eon paid $1.2 million to design the X5000 and A1222+ hardware.

https://web.archive.org/web/20140328052600/http://www.a-eon.com/18-10-2013-3.pdf

A-Eon may be paying creditors 566k £ a year judging from UK filed financial statements.

A-EON TECHNOLOGY LTD
https://find-and-update.company-information.service.gov.uk/company/08020555/filing-history

The UK government site also reveals that Matthew Leamen is the director of A-Eon and owns 25%-50% of the A-Eon stock.

A-EON TECHNOLOGY LTD
https://find-and-update.company-information.service.gov.uk/company/08020555/persons-with-significant-control

I expect Trevor has financed other A-EonKit businesses and Hyperion as well as lawsuits.

AMIGA TECHNOLOGY LTD
https://find-and-update.company-information.service.gov.uk/company/10732120/persons-with-significant-control

AMIGAKIT LTD
https://find-and-update.company-information.service.gov.uk/company/11916748/persons-with-significant-control

LEAMAN COMPUTING LIMITED
https://find-and-update.company-information.service.gov.uk/company/06865537/persons-with-significant-control

They have more shell businesses than Ben Hermans. Has Trevor found a more reliable partner to challenge Amiga IP ownership than Ben?

A bunch of money wasting suckers.

Imagine if all that money instead had been used to support development of AROS on conventional off-the-shelf hardware and "classic" 68k hardware, instead of wasting it on development of hardware that is doomed to be low volume, super expensive and old before it is even ready.

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You guys and your silly fights are something else!

Motorla has already given you the answer on what is the best architecture.

That's why millions of MOTOROLA set-top cable boxes from the early 2000's use

....
68k?
Coldfire?
PPC?
....



6502... The one cpu that rules them all!


https://retro-hardware.com/2017/01/06/6502-in-millions-of-tv-set-top-boxes-across-north-america-or-cracking-satellite-and-cable-pay-tv/

Long live the 6502!
Oh that's right ... it still lives ... unlike the boat-anchor cpu(s) you guys are defending...

Perhaps if AROS was ported to the 65816 or 65CE02, more people would care about AROS.

What's an Amiga without it's chipset?
An underclocked Atari.

Why did Amiga lag behind?
It's cpu and it's chipset.

The 3.57Mhz 8/16bit 65CE02 C65 was outperforming the Amiga 500 and they didn't want to cut into Amiga sales so they cancelled it. In 1990, it was doing 640x400x16 320x200 256 color graphics before AGA and could have competed against the SNES.

https://www.youtube.com/watch?v=OoHxDe3Gc9E

Keep fighting amongst yourselves...
See you in a month!

@matthey

Quote:

matthey wrote: agami Quote: Very sadly. Which opened him up to bad technical advice, from people looking to further their own agenda. Not very sadly for him. Every investor should follow the 1st rule of investing: Never invest money you're not OK with losing. So I hope he enjoys his A-EON X5000/40 with a paltry PPC software library. It only cost him $500k. Very sadly for us, because his misguided efforts did not do anything to eliminate the divide in the Amiga community, it took up way too much of the limited oxygen in the proverbial room, and after 15 years we have little to show for it. Trevor has spent more than "$500k" for his X5000 hobby. A-Eon paid $1.2 million to design the X5000 and A1222+ hardware.

I'm stating rough NET cost for that particular SKU. He did recover some of the $2M+ since 2009 with sales of X1000, X5000, SAM460 LE, and A1222+ units.

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@NutsAboutAmiga

Quote:

NutsAboutAmiga wrote: @agami Genius compared to using high end FPGA’s that’s for sure.

It's also "genius" compared to waiting for some future quantum computing core. There's more choices than just expensive EoL PPC, and more expensive FPGA.

If I were his advisor at the time, he would've started with a PPC card on an AMD AM3 system, and by now he'd be selling either x86 or ARM systems running an A-EON AROS distro, a la Amibench.

So no, not genius.

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@kolla

Quote:

kolla wrote: A bunch of money wasting suckers. Imagine if all that money instead had been used to support development of AROS on conventional off-the-shelf hardware and "classic" 68k hardware, instead of wasting it on development of hardware that is doomed to be low volume, super expensive and old before it is even ready.

Thanks for pouring salt on a wound that refuses to heal.

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