Quote:

Very nice. There's almost no software for OS4 that uses Altivec, it's mostly scalar one.

Scalar performance is not a strong point for STI’s Cell.

Quote:

I'm not talking about a compiler that "magically" starts to use al SPEs, but simply recompiling the current code so instructions are ordered correctly.

Factor in unrolling loops and replace branchy code with non-branch code.

There are complier limits for in-order, weak branch features and relatively deep pipelined architecture (Pentium IV Northwood level deep).

As an example for replacing branch code, refer to
"Choosing to Avoid Branches: A Small Altivec Example"
http://www.cellperformance.com/articles/2006/04/choosing_to_avoid_branches_a_s.html

Quote:

What application you plan to run on OS4 that would run slow? The farting button? IBrowse? YAM? Come on, these apps already ran quite fast with a 060/50Mhz, don't tell me that a CELL will be worse than a 800¤ ArticiaS+G4. I don't believe that it's going to be slower than a DiscoveryII+G4/1Ghz either.

I don’t see OS4 being run on existing PPC G5 Macs (with PPC Linux), let alone on the 'freebee' CellSim (Cell simulator) software.

_________________
Amiga 1200 (rev 1D1, KS 3.2, PiStorm32/RPi CM4/Emu68)
Amiga 500 (rev 6A, ECS, KS 3.2, PiStorm/RPi 4B/Emu68)
Ryzen 9 7900X, DDR5-6000 64 GB RAM, GeForce RTX 4080 16 GB

@Hammer

Quote:

Scalar performance is not a strong point for STI’s Cell.

Yeah, but it will be better than an ArticiaS+G3/800Mhz, recompiling or not.

_________________
The only spanish amiga news web page/club: CUAZ

Quote:

Yeah, but it will be better than an ArticiaS+G3/800Mhz, recompiling or not.

Depends if existing OS4 PPC G3 apps avoids PPE microcoded ops.

PPE microcoded ops include:
1. CR recording instructions (Rc=1)
2. Shift and rotate instructions where the shift amount is source from a register (as opposed to an immediate value encoded in the instruction)
3. Load and store algebraic, multiple, and string instructions
4. Misaligned accesses including Dcache accesses that cross 32-byte boundaries and double floating-point loads and store to an odd word boundary.

When a microcoded op is encountered by either HW thread, both threads are stalled.

Due to pipeline depth and weaker OOOE frontend, its recommended the program exploits SMT. Can OS4 maximize SMT?

Note that Apple have objected the CELL processor due to significantly lower single-threaded scalar performance than the PowerPC 970. In certain applications, PowerPC 970 is noted to be less efficient than its’ medium pipeline length OOOE PPC G3/G4 brethren i.e. PowerPC 970xx relies on clock speed and bandwidth.

I wouldn’t comment on ArticiaS.

Last edited by Hammer on 22-Oct-2006 at 02:19 AM.
Last edited by Hammer on 22-Oct-2006 at 02:16 AM.

_________________
Amiga 1200 (rev 1D1, KS 3.2, PiStorm32/RPi CM4/Emu68)
Amiga 500 (rev 6A, ECS, KS 3.2, PiStorm/RPi 4B/Emu68)
Ryzen 9 7900X, DDR5-6000 64 GB RAM, GeForce RTX 4080 16 GB