@Hammer

Quote:

1. Atomic instruction that is executed close to 1 instruction per cycle or greater.

ATOMIC instructions is a term for special instructions used for syncing two tasks.


Quote:

2. Fix length instructions are important for pipelining.

No, fixed length has no influence on pipelining.
The pipelining and tracking of instruction is never done in the "original" encoding but in an internal format.

Fixed length help decoding of a second instruction simpler.



Quote:

3. RISC's atomic load and store instructions ideology is less important.

Again "ATOMIC" instructions is the term for instruction like TAS or CAS which are used to create mutexes.



Quote:

4. RISC world's pure register-only math operations. Who cares.

This is very important for a RISC CPU.



The whole point of doing a RISC CPU is to save a lot of effort during CPU development.
The saved effort = saved time.

This saving comes from having less variant of instructions that need to be verified.
This is simple math.


Lets say you have 100 instruction.
And you support 1 address mode = register. Then its 100*1 = 100
Then your basic testing effort is 100 testcases.

OK now you want to be Super-Scalar and do 3 instructions parallel.
100*100*100
=1 Million testcases.

Lets say you have 100 instructions on CISC
and you have 4 sizes Byte/Word/Long/Quad.
Now you have 400 tests needed.
And you support 14 Address modes.
400*14 = 5600 tests needed.

Now you want to be Super Scalar and do 3 instructions in parallel
5600*5600*5600 = 175.616.000.000 testcases needed


RISC reduce the number of needed testcases,
this simplification does saves many month / years development time.

@cdimauro

Quote:

Intel has published direct SSE versus AVX comparisons with benchmarks run on the same second-generation Core i7 processor with FFT performance improvements ranging from 1.2 to 1.8x.

Intel Core i3 N series 100% Gracemont E-Cores don't have native 256-bit hardware units.

Intel's Thread Director is a workaround to minimize E-Core's involvement with modern PC games.

IBM POWER8's VSR has 64 128-bit SIMD registers which have a total of 8,192 bits at the front end. POWER8 was launched in 2014.

POWER8 8 E4E5 's six cores (up to 48 SMT) @ 4.1 Ghz are relatively cheap, but the problem is the low-cost motherboard with 1 PCIe 16X slot and 2 to 3 PCIe 1X slots.
Should have open-source POWER8 motherboard design for unrestricted clones.

POWER8 can be configurated with SMT8, SMT4, SMT2, SMT1 (ST) modes.

Per POWER8 has 16 execution units:
2 Fixed point units.
2 Load store units (can also execute simple fixed-point operations).
2 Load units (can also execute simple fixed-point operations).
4 Double precision floating point (can act as eight single-precision pipelines).
2 Vector unit 128-bit VMX/AltiVec.
1 Crypto (AES).
1 Branch.
1 Condition register.
1 Decimal floating point unit.
From https://www.7-cpu.com/cpu/Power8.html

Intel SkyLake X was launched in 2017.
Intel Haswell was launched in 2023.

From the front-end instruction set, IBM POWER8 (8,192 bits) has the edge over Intel's Haswell's 16 registers 256-bit AVX2 (4,096 bits), but Haswell has two FMA3 256-bit AVX units.

Intel Haswell's implementation has the following vector execution engines
Port 0, 256-bit FMA with FBlend, 256-bit VMUL/VShift
Port 1, 256-Bit FMA with FADD, 256-Bit VALU with FBlend
Port 5, 256-Bit FShuffle with FBlend, 256-bit VALU VShuffle

Intel Haswell also has HD 4000 IGP with up to 332.8 GFLOPS FP32.

The instruction set may not reflect the actual hardware implementation.

Last edited by Hammer on 18-Mar-2024 at 06:24 AM.

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@cdimauro

Quote:

The first edition came on 1985, right? When both machines weren't released.

Correct the first edition did came out with the A1000 and before the A500,

This book was the bible that all Amiga developers did read.

Every Amiga coder that wrote games for or demos did read this book.

Basically all the developers that wrote games for Amiga,

games like MENACE, HYBRIS, TURRICAN, GIANA SISTERS ..

they all learn how to code the Amiga hardware using this book.

And this book teaches pretty well how to code the hardware directly.

@Gunnar

Quote:

ATOMIC instructions is a term for special instructions used for syncing two tasks.

From the Greek meaning "not divisible into smaller parts".

An "atomic" operation is always observed to be done or not done, but never halfway done.

An atomic operation must be performed entirely or not performed at all.

In multi-threaded scenarios, a variable goes from unmutated to mutated directly, with no "halfway mutated" values.

Quote:

No, fixed length has no influence on pipelining.

The fixed length has influenced on pipelining i.e. reduced complexity and reaching higher clock speed. Refer to DEC Alpha's RISC concept.

Quote:

Again "ATOMIC" instructions is the term for instruction like TAS or CAS which are used to create mutexes.

I was referring to the Greek meaning "not divisible into smaller parts".

Quote:

This is very important for a RISC CPU.

For X86 world, who cares.

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@Hammer

Quote:

Hammer wrote: @cdimauro Quote: Have you ever OPENED Intel's or AMD's OPTIMIZATION MANUALS? Maybe you'll find something which, unfortunately for you, gives a completely different picture of what you think about this argument. Intel has "128-bit AVX" and "AVX128" (e.g. page 2-25, page 3-62) in "Intel @ 64 an IA-32 Architecture Optimization Reference Manual" with Order Number: 248966-046A. January 2023

From the same manual, regarding those parts:

Figure 15-1. Intel® AVX—Intel® SSE Transitions in the Broadwell, and Prior Generation Microarchitectures
Execute Intel SSE Execute 256-bit or 128-bit Intel AVX
Execute 256-bit Intel AVX
Execute 256 or 128 Bit Intel AVX Penalty B
Execute 256-bit or 128-bit Intel AVX
[...]
lists the effect of mixing Intel AVX and Intel SSE code, with the bottom row indicating the
types of penalty that might arise depending on the initial YMM state (the row marked ‘Begin’) and the
ending state. Table 15-2 also includes the effect of transition penalty (Type C and D) associated with
restoring a dirty YMM state image stored in memory.
[...]


Figure 15-2. Intel® AVX- Intel® SSE Transitions in the Skylake Microarchitecture
Execute SSE or 128-bit AVX
Execute 256-bit or 128-bit AVX
Execute 256-bit AVX
[...]
Table 15-2. State Transitions of Mixing AVX and SSE Code
Execute SSE
Execute AVX-128
Execute AVX-256
[...]
The magnitude of each type of transition penalty can vary across different microarchitectures. In Skylake
microarchitecture, some of the transition penalty is reduced. The transition diagram and associated
penalty is depicted in Table 15-2. Table 15-3 gives approximate order of magnitude of the different transition penalty types across recent microarchitectures.


[...]
Example 15-32. Single-Precision to Half-Precision Conversion
AVX-128 code
[...]
Example 15-32 compares two implementations of floating-point conversion from single precision to half
precision. The code on the left uses packed integer shift instructions that is limited to 128-bit SIMD
instruction set. The code on right is unrolled twice and uses the VCVTPS2PH instruction
[...]
The code using VCVTPS2PH is approximately four times faster than the AVX-128 sequence. Although it is
possible to load 8 data elements at once with 256-bit AVX, most of the per-element conversion operations require packed integer instructions which do not have 256-bit extensions yet. Using VCVTPS2PH is
not only faster but also provides handling of special cases that do not encode to normal half-precision
floating-point values.
[...]


Table 2-10 includes information about the maximum Intel® Turbo Boost technology core frequency for
each type of instruction executed. The maximum frequency (P0n) is an array of frequencies which
depend on the number of cores within the category. The more cores belonging to a category at any given
time, the lower the maximum frequency.
[...]
Intel® AVX2 light instructions
Instruction Types: Scalar, AVX128, SSE, Intel® AVX2 w/o FP or INT MUL/FMA


[...]
Table 3-5. Relative Performance of Memcpy() Using Enhanced REP MOVSB and STOSB Vs. 128-bit AVX
Memcpy_ERMSB/Memcpy_AVX128
[...]
Table 3-5 shows the relative performance of the Memcpy function implemented using enhanced REP
MOVSB versus 128-bit AVX for several ranges of memcpy lengths, when both the source and destination
addresses are 16-byte aligned and the source region and destination region do not overlap. For memcpy
length less than 128 bytes, using Enhanced REP MOVSB and STOSB is slower than what’s possible using
128-bit AVX, due to internal start-up overhead in the REP string


Those are ALL the references about AVX-128, AVX-256, AVX128 and AVX256 which are found in that manual and all of them belong to the MICROARCHITECTURE, as it's clearly reported even in the manual by USING EXACTLY THIS TERM!

So, we're NOT in the ISA = Instruction Set Architecture = Architecture domain! That's the MICROARCHITECTURE domain!

You continue to mix both things because you do NOT UNDERSTAND, at all, such technical things. Which are clearly outside of your limited capacities. You're HOPELESS!
Quote:

Idiot.

Me? Look above, insane!

You continue to have no clue at all of the topic, since you continue to completely mix (and do NOT understand) ISA = Instruction Set Architecture and Microarchitectures.
Quote:

AVX128 is a shortened term for "128-bit AVX".

Which is a short them for... AVX's 128 bit instructions.

Which are PART of the ISA = Architecture, since the ISA defines 128 AND (highlighted only for YOUR convenience) 256 bit instructions. Yes, AVX defines BOTH of them. And ANY processor which is implementing it supports and executes BOTH type of instructions.
Quote:

I don't hide behind "256-bit AVX" front-end instruction set marketing.

Frontend = MICROarchitecture.

You continue to mix APPLES and ORAGES. Hopeless...


What's even worse, is that I've mentioned the Optimization manuals for a COMPLETELY DIFFERENT argument, since in THIS part of the discussion the topic was the RISCs vs CISCs comparison. Which you don't know as well, as you've shown again.

Anyway, in THIS point the mention is because you've to take a look at how the processors are implemented = MICROARCHITECTURE. That's to see that they have NOTHING to do with a internal RISC.

Read again: you look at the Optimization manuals to UNDERSTAND that there's NO internal RISCs. Since they internally work DIFFERENTLY

E.g.: look at your beloved AMD MACROOPS: they CANNOT BE classified as "RISC instructions". AT ALL! IF you understand how they are made and how they are executed.


So, you COMPLETELY LOST the context in this part of the discussion. You're insane! And hopeless!

@cdimauro

Quote:

Those are ALL the references about AVX-128, AVX-256, AVX128 and AVX256 which are found in that manual and all of them belong to the MICROARCHITECTURE, as it's clearly reported even in the manual by USING EXACTLY THIS TERM! So, we're NOT in the ISA = Instruction Set Architecture = Architecture domain! That's the MICROARCHITECTURE domain! You continue to mix both things because you do NOT UNDERSTAND, at all, such technical things. Which are clearly outside of your limited capacities. You're HOPELESS!

For transparency, my argument is MICROARCHITECTURE.

Your instruction set focus hides the actual MICROARCHITECTURE implementation!

When I used AMD Jaguar's example, I was referring to the MICROARCHITECTURE implementation to debunk your stupid "256-bit AVX" instruction set marketing.

I don't support 256-bit AVX instruction set marketing when its corresponding 256-bit hardware is NOT guaranteed by Intel e.g. Gracemont MICROARCHITECTURE. AMD has abandoned 128-bit SIMD-equipped CPUs.

You can jump up and down about AVX's "256-bit" superiority and it wouldn't change the fact that Intel regressed into a 128-bit hardware implementation.

---------

From the surface, IBM POWER8's 64 128-bit VSR register's total size is 8,192 bits which is superior when compared to Intel's 16 registers 256-bit AVX/AVX2's 4,096 bits.

Did you forget IBM's POWER8 VSR improvements?


https://www.ibm.com/support/pages/vectorizing-fun-and-performance
POWER8 has 64 "vector-scalar registers' (VSRs), the first 32 of which are shared space with the 32 floating point registers. Each VSR is 128-bit.

For vector data register storage at the instruction set architecture level, POWER8 was superior until SkyLake X's AVX-512 release during the year 2017.

Instruction set architecture with performance debate is nearly meaningless when MICROARCHITECTURE's design is factored in.

Last edited by Hammer on 18-Mar-2024 at 07:34 AM.
Last edited by Hammer on 18-Mar-2024 at 07:18 AM.
Last edited by Hammer on 18-Mar-2024 at 06:21 AM.

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@Hammer

Quote:

Again "ATOMIC" instructions is the term for instruction like TAS or CAS which are used to create mutexes.

Quote:

I was referring to the Greek meaning "not divisible into smaller parts".

The point of TAS / CAS is to use special BUS cycles that are not divide-able.

@cdimauro

Quote:

Frontend = MICROarchitecture.

The front end contains the logical instruction set architecture's register set enforcement e.g. 16 register programming model behavior.

The programmer doesn't have access to the larger register count from register renaming hardware.

Quote:

You continue to have no clue at all of the topic, since you continue to completely mix (and do NOT understand) ISA = Instruction Set Architecture and Microarchitectures.

Again, your 256-bit AVX instruction set argument is useless when the current Intel administration doesn't even guarantee corresponding 256-bit hardware across its latest CPU products.

Stop drinking the marketing cool-aid.

Last edited by Hammer on 18-Mar-2024 at 06:38 AM.

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@Gunnar

HAMMER:
Quote:

2. Fix length instructions are important for pipelining.

GUNNAR:
Quote:

No, fixed length has no influence on pipelining.

HAMMER:
Quote:

The fixed length has influenced on pipelining

No its does not.
This has nothing to do with each other.


Pipelining is the term for "dividing" the amount of work an instruction does into smaller step.
As smaller the step you make, as higher can your clock be.
Every CPU can do pipelining - both RISC and CISC do pipelining.


During the pipelining the CPU keep track of all instructions.
All CPU do this both RISC and CISC.
The keeping track during pipelining of instructions is always done in an internal "format"
This internal format has nothing todo with how the instructions look for the programmer.

As you know 68k instructions can be between 2 and 22 Byte long.
During pipelining the signals and information the CPU tracks are all same size.


The fixed length instructions make decoding of several instructions per cycle simpler.

To decoder 2 instruction you need to know where the 2nd instructions starts.
For 68K instruction which are 2..22 byte long, the 2nd instruction can start at many places.
CPU with variable length have the problem they need to first find our where the 2nd instruction begins before they can decode it. Same problem if you want to decoder 3 or 4 instructions per cycle.
But this problem is solveble.

Fixed length instruction set CPUs not have this problem.

@cdimauro

Quote:

So, you COMPLETELY LOST the context in this part of the discussion. You're insane! And hopeless!

Even if Hammer mixed up some stuff.
Why do you need to get personal again?

@Gunnar

Quote:

Pipelining is the term for "dividing" the amount of work an instruction does into smaller step. As smaller the step you make, as higher can your clock be.

That's one aspect of it. Zen 4C's compact size has lowered its high clock speed potential when compared to the larger area size Zen 4.

Both Zen 4C and Zen 4 have the same pipeline stages.

My secondary CCDs for my Ryzen 9 7950X and Ryzen 9 7900X have lower clock speeds when compared to the 1st "good" CCD silicon.

Better quality silicon (silicon lottery) has higher clock speed potential.

My 68060 Rev 1 can reach 62.5 Mhz without any problems while other well-known YouTuber's 68060 Rev 5 couldn't get past 60 Mhz.

My 68060 Rev 1 is partly stable at 74 Mhz before locking up. My other $30 68LC060 Rev 4 can reach 74 Mhz and it was shipped with my TF1260.

Quote:

Every CPU can do pipelining - both RISC and CISC do pipelining.

Classic Pentium has a superscalar pipeline design.

68060's FPU wasn't pipelined.

From Stanford University

Why is RISC better for pipelining?

Pipelining
Because RISC instructions are simpler than those used in pre-RISC processors (now called CISC, or Complex Instruction Set Computer), they are more conducive to pipelining. While CISC instructions varied in length, RISC instructions are all the same length and can be fetched in a single operation.

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@Hammer

GUNNAR
Quote:

Pipelining is the term for "dividing" the amount of work an instruction does into smaller step. As smaller the step you make, as higher can your clock be.

Year 2001

CISC Pentium 4 = 2000 MHz
RISC G4 Motorola = 800 MHz.

What do you see?



The instruction set length is not important.
What is important for reaching high clockrate is the pipeline length

If you make a longer pipeline then you can reach higher clock.
Two famous very high clockrate CPUs are Pentium 4 and CELL


The main point about RISC is - that they are easier to make.
They need less time to design and to verify - and this saves the company making them time and money.

This is an advantage mainly for the company making them not necessarily for the customer.

RISC CPUs also have design disadvantages.
As the RISC instructions do less work you often need MORE instruction for doing the same as a CISC instruction.

Famous examples:

ADD.l #$123456,myvariable

This is one instruction for an 68K, this is 10 byte in length.
To do the same you need like 5 instruction on PowerPC or other RISC and 20 Byte in length.

RISC code needs often more bytes.
This makes your caches less effective = this is a big disadvantage!

Of course as the RISC CPU needs more instruction CISC CPU can get here also a performance advantage.



RISC CPU DESIGN is a trade-off
The RISC CPU has some disadvantages mainly for the users, the customers
but they give the manufacturer a big advantage that they are faster and cheaper to design and to verify.

Last edited by Gunnar on 18-Mar-2024 at 07:30 AM.

@Hammer

GUNNAR:
Quote:

Every CPU can do pipelining - both RISC and CISC do pipelining.

HAMMER:
Quote:

Classic Pentium has a superscalar pipeline design. 68060's FPU wasn't pipelined.

Both are CISC CPU.

I know what you want to say but you say it not fully correct.

Let me help you:

* Both Pentium and 68060 are super scaler integer design.

* Both the Pentium FPU and the 68060 FPU are actually pipelined but to different degree.

- The 060 FPU is partly pipelined and
some FPU instructions are single cycle FCMP/ FNEG / FABS ...
instruction like FADD/FMUL need 3 cycle (only)
FDIV needs 39 cycle
FSQRT need 68 cycle

- The Pentium FPU is more pipelined and instructions like FADD/FMULL need 1 cycle (only)
The Pentium FPU is NOT fully pipelined!
Instructions like FDIV need 39 cycle and FSQRT need 70 cycle!

- A lot more pipelined is the Apollo 68080 FPU.
The Apollo FPU is fully pipelined and can even finish on FDIVIDE and FSQUAREROOT per clock cycle


As you see the APOLLO 68080 FPU design is a lot more advanced than the PENTIUM FPU.

Any CPU either CISC or RISC can use pipelining.

Last edited by Gunnar on 18-Mar-2024 at 09:50 AM.
Last edited by Gunnar on 18-Mar-2024 at 08:03 AM.

@Gunnar

Quote:

CISC Pentium 4 = 2000 MHz RISC G4 Motorola = 800 MHz.

Pentium IV Wilamette has a fixed-length micro-OP and 20-stage long pipeline.

For apples to apples using the same Motorola's 130 nm SOI process tech,

PowerPC 7447 @ 1.33 Ghz was fab'ed on Motorola's 130 nm SOI process. PowerPC 7447A reached 1.67 Ghz.

AMD licensed Motorola's 130 nm SOI process tech for Athlon 64 CPUs and its fastest SKU was 2.4 Ghz Athlon 64 4000+.


Quote:

Two famous very high clockrate CPUs are Pentium 4 and CELL

AMD's Piledriver FX-9590 delivered a 5Ghz SKU into retail.

Piledriver has a 20-stage long pipeline similar to Pentium IV Wilamette/Northwood's 20-stage level.

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@Hammer

Quote:

Pentium IV Wilamette has a fixed-length micro-OP and 20-stage long pipeline. For apples to apples using the same Motorola's 130 nm SOI process tech, PowerPC 7447 @ 1.33 Ghz was fab'ed on Motorola's 130 nm SOI process. PowerPC 7447A reached 1.67 Ghz. AMD licensed Motorola's 130 nm SOI process tech for Athlon 64 CPUs and its fastest SKU was 2.4 Ghz Athlon 64 4000+.

That "fixed length" instructions are needed for high clock rate is a MYTH

High clock rate does depends only on pipeline length and process used.

@Gunnar

Quote:

Year 2001 CISC Pentium 4 = 2000 MHz RISC G4 Motorola = 800 MHz. What do you see?

Compare cooling!

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@ppcamiga1

Attacks on hardware are senseless.

However, as ex x1000 user, I can say one should be unhappy how
OS4 does not fully utilize hardware at disposal.

PPC transition was OK for the time, but too little was archived - OS4
is not as good as MorphOS in hardware supported and many features
(even OS3/WOS compatibility in practice) except with modern Radeon drivers, thanks to Mr. Hans.

Also tactics of too many announcements (OS 4.2, TW, Libre ...) and too much milking (FE, Enhancer, separate drivers purchase).

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@Gunnar

Quote:

 A lot more pipelined is the Apollo 68080 FPU. The Apollo FPU is fully pipelined and can even finish on FDIVIDE and FSQUAREROOT per clock cycle

How many cycles do these need in total?

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@vox

Quote:

(even OS3 compatibility in practice)

MorphOS does not support NallePuh this only work on AmigaOS4,
NallePuh adds support for hardware bagging, if it was worth it I do not know.
MorphOS does handled some legacy API calls better for legacy software true.
more or less the same.

Quote:

(even WOS compatibility in practice)

WOS support comes in 3 flavors for AmigaOS4, support added, dropped, reimplemented, and reintroduced in Enhancer. So its complicated, should be fine now.

It really is none issue, as not many things that’s WOS, a few demos at tiny resolutions, a few games, many of games now has OS4 native version like WipeOut, Hertic II, FreeSpace, etc.. sure there is few games, but you can’t buy the games anymore in web stores so who cares. (The Feeble Files, Nightlong: Union City Conspiracy)

it used to be more important, now its simply not.

Somes games has a 68K and WOS version, and you can’t tell the difference, example the game PayBack.

Last edited by NutsAboutAmiga on 18-Mar-2024 at 07:58 PM.
Last edited by NutsAboutAmiga on 18-Mar-2024 at 07:53 PM.
Last edited by NutsAboutAmiga on 18-Mar-2024 at 07:51 PM.
Last edited by NutsAboutAmiga on 18-Mar-2024 at 07:50 PM.
Last edited by NutsAboutAmiga on 18-Mar-2024 at 07:47 PM.

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@NutsAboutAmiga

In practice, a lot of clean WB software, simply does not work on OS4 but does work on MOS.
There is part of software that does exist for PowerUp and WOS but does not exist on 68k *mainly plugins etc. so to some people its relevant. I see Hyperion charging again for same software, just being OS4 friendly (Heretic 2, Shogo ...). They should better release Sin!, Worms Armageddon and some other promised games :D As well OS 4.2 x1000 users did prepay for.

On PayBack: It does not work properly under OS4, I have tried, even with latest updates. Does Petunia have penalty to native PPC software? I suppose to some extent.

Enhancer is not official part of OS4 and best to my knowledge WOS support is not reimplemented. Warp3D support is.

NallePuh is not part of OS4 and is not perfect Paula replacement. Tried to use NallePuh and CIA Agent to make OS4 more Amiga friendly, but did not help.

Instead of Xena some FPGA OCS/AGA implementation should be onboard.

Its all nice and dandy on paper, until you actually try it.
PPC native library of MorphOS is comparable or even bigger then of OS4.

Not to be completely OS4 negative, I liked the look and OS4 0 Classic theme (more then OS 4.1 and FE), as well as some OS4 specific software like Emotion. Leveling up MUI to MUI4 (with fake MUI5) is also nice, but I doubt is it with authors approval. Quite a legal mess, and could be executed way better. On side-note, I wonder how much more progress would be made if MorphOS was made official.

Last edited by vox on 18-Mar-2024 at 09:35 PM.
Last edited by vox on 18-Mar-2024 at 09:06 PM.

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